用于数字电视调谐器的宽带CMOS VCO设计

采用片外谐振网络和多VCO的结构设计了一个宽带CMOS VCO,并采用一种新型的电荷泵式自动幅度控制电路,确保了VCO在整个带宽内的可靠性。基于Chartered 0.25μm CMOS工艺的测试结果表明,该VCO的频率能够覆盖75~900 MHz,单边带相位噪声最佳值达到了-92 dBc/Hz@10 kHz。     

基于0.18μm SiGe BiCMOS工艺的60GHz VCO分析与设计

采用0.18 μm SiGe BiCMOS工艺,设计了一个60GHz的交叉耦合差分压控振荡器(VCO).通过分析传输线的性能,用λ/ 4短路传输线构造谐振回路.在分析VCO相位噪声的基础上,采用噪声滤波技术提高VCO的相位噪声性能.该VCO的工作电压为2.2V,偏置电流为11mA,频率调谐范围为58.377GHz～60.365GHz.当振荡频率为60.365GHz时,1MHz和10MHz频偏处的相位噪声分别为-79.1dBc/ Hz和-99.77dBc/ Hz.     

低相位噪声VCO的设计

设计了一个用于移动通信中继站的低相位噪声压控振荡器(VCO)。该VCO采用了考皮兹结构,谐振器使用LC器件,放大器件使用双极结型晶体管(BJT)。其频率调动范围为730～840 MHz,压控灵敏度为22 MHz/V,输出功率为10.7 dBm。在800 MHz中心频率处,其实测相位噪声分别为-99.42 dBc/Hz@10 kHz,-116.44 dBc/Hz@100 kHz,-135.06 dBc/Hz@1 MHz。提出了一种采用基极低频滤波的办法消除VCO的杂散频率,整个测试频段内观察不到明显的杂散。阐述了VCO相位噪声的主要来源,给出了低噪声VCO的设计方法。理论计算,仿真结果和实物测试取得了一致的结论,对低噪声VCO的设计提供了一定的参考。     

一个2.2GHz低相位噪声的高频率LC压控振荡器的设计

为了满足高性能锁相环对高频压控振荡器低相位噪声的要求,提供了CMOS全集成负电导压控振荡器在2.2 GHz频率的设计。这种结构的优点和缺点要在设计中相互平衡。CMOS VCO的相位噪声应用据线性时变脉冲敏感函数(ISF)分析和计算并且与仿真结果进行比较。结果证明线性时变模型ISF能够很好的估算相位噪声,同时使用LC滤波技术改善相位噪声性能,在1/f3区域,相位噪声改善了9 dBc/Hz;在1/f2区域,改善了5 dBc/Hz。在最后给出使用0.35μmCMOS工艺制作的2.2 GHz VCO的实验结果。     

一种高性能全差分双环路VCO的设计

设计了一种基于SMIC 0.18μm RF 1P6MCMOS工艺的高性能全差分环形压控振荡器(ring-VCO),采用双环连接方式,并运用交叉耦合正反馈来提高性能。在1.8V电源电压下对电路进行仿真,结果表明:1)中心频率为500MHz的环形VCO频率调谐范围为341～658MHz,增益最大值Kvco为-278.8MHz/V,谐振在500MHz下VCO的相位噪声为-104dBc/Hz@1MHz,功耗为22mW;2)中心频率为2.5GHz的环形VCO频率调谐范围为2.27～2.79GHz,增益最大值Kvco为-514.6MHz/V,谐振在2.5GHz下VCO的相位噪声为-98dBc/Hz@1MHz,功耗为32mW。该VCO适用于低压电路、高精度锁相环等。     

GPS接收机中1.57 GHz CMOS锁相环的设计

设计了一种用于GPS接收机中采用CMOS工艺实现的1.57GHz锁相环.其中,预分频器采用高速钟控锁存器(LATCH)的结构,工作频率超过2GHz.VCO中采用LC谐振回路,具有4段连续的调节范围,输出频率范围可以达到中心频率的20%.电荷泵采用一种改进型宽摆幅自校准电路,可以进一步降低环路噪声.锁相环采用0.25μmRFCOMS工艺实现.测量表明VCO输出在偏移中心频率1MHz处的相位噪声为-110dBc/Hz,锁相环输出在偏移中心频率10kHz处的相位噪声小于-90dBc/Hz.供电电压为2.5V时,功耗小于15mW.     

基于栅极电感反馈的CMOS差分Vacker VCO设计

提出了一种基于栅极电感反馈的Vacker压控振荡器(VCO),该结构能够改善电路的负阻抗,进而使得电路易于起振。对晶体管的负载效应和振幅稳定性的分析表明,该Vacker VCO相比较于Colpitts VCO,具有更好的振幅稳定性,进而改善了VCO的相位噪声。基于0.13-μm RF CMOS工艺,对该Vacker VCO进行了设计与芯片实现,测试结果表明：在消耗4.2 mW功耗的前提下,该VCO振荡频率为11 GHz～12.6 GHz,在11.8 GHz振荡频率处,相位噪声为-115.1 dBc/Hz@1 MHz,品质因数FOM指标达到-190.3 dBc/Hz。     

双耦合跨导增强型低功耗压控振荡器

设计了一种工作于Ku波段和Ka波段的新型电容电感压控振荡器(LC VCO),具有低功耗和低相位噪声的优点。Ku波段的信号由交叉耦合LC VCO产生,在此基础上利用PMOS push-push倍频器结构,将信号频率由Ku波段扩展到Ka波段。采用互补型交叉耦合对结构,通过电流复用技术,提高信号的输出摆幅。同时该结构通过电容分裂技术和栅极漏极阻抗平衡技术,降低了功耗和相位噪声。该双频段VCO芯片基于0.13μm CMOS工艺实现,尺寸为0.88 mm×0.64 mm。测试结果表明,在1.25 V电源电压下,该VCO的功耗为2.25 mW。14.53 GHz时,该VCO在偏移中心频率1 MHz和10 MHz处的输出相位噪声分别为-115.3 dBc/Hz和-134.8 dBc/Hz, 29.08 GHz时的输出相位噪声分别为-109.67 dBc/Hz和-129.23 dBc/Hz。     

3.1~4.9 GHz宽带低相位噪声频率源的研制

基于LTC6946-2频率合成器设计了3.1~4.9 GH频率源,给出了参数设计过程和实物测试结果。该频率源具有宽带、低相位噪声、低杂散、低成本和占用面积小等特点。经过硬件调试达到的主要指标为:输出频率3.1~4.9 GHz,步进10 MHz,相位噪声优于-97.8 dBc/Hz@1 kHz和-99.3 dBc/Hz@10 kHz,杂散优于-90 dBc。     

一种低压低相位噪声的C类VCO

提出了一种低压低相位噪声的C类VCO电路。低压条件下,基于振幅反馈环的C类VCO存在振幅小、相位噪声差的问题,可以通过移除尾电流源、增加低通滤波器等方式来改善相位噪声。基于SMIC 0.18 μm CMOS工艺,采用Cadence Spectre EDA软件对VCO进行仿真。结果表明,当载波频率为2.27 GHz时,在1 MHz频偏处VCO的相位噪声为-126 dBc/Hz,在供电电压为0.9 V时,功耗仅为2.5 mW,FOM值为-189 dBc/Hz。     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range

A 900-MHz fully integrated VCO was fabricated in a 0.18-/spl mu/m foundry CMOS process. Under 1.5 V power supply, this VCO can be tuned from 667 MHz to 1156 MHz which corresponds to a 53.6% tuning range. The VCO has nearly constant phase noise over the whole tuning frequency, credit to the switched resonators used in this VCO. The phase noise at a 600 kHz offset is -123.1 dBc/Hz at 1125 MHz center frequency and -124.2 dBc/Hz at 667 MHz center frequency.     

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance.The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured tuning range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply.The whole silicon required is only 0.53 mm~2.     

一种应用于低噪声PLL的RF-VCO设计

在PLL电路设计中,压控振荡器设计是电路的关键模块,按类型又主要分为LC震荡器和环形振荡器两种,其性能直接决定了相位噪声、频率稳定度及覆盖范围。文章介绍了一款1.8 GHz的基于交叉耦合对LC结构的低噪声CMOS压控振荡器的设计,并对调谐范围、相位噪声以及电路起振条件等做了分析讨论。该设计采用0.18μm 6层金属CMOS工艺制造,模块面积为0.3 mm2,电路经过Cadence SpectreRF仿真,VCO的输出范围为1 594~2 023 MHz,中心频率1.8 GHz输出时相位噪声为-118 dBc/Hz@600 kHz,1.9 GHz输出时相位噪声为-121 dBc/Hz@600 kHz。结果表明该VCO设计达到了较宽的频率覆盖范围和较低的相位噪声,可以满足低噪声PLL的设计要求。     

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCO's output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35 µm process show a linear tuning range improvement of 75% of the control voltage in the (1.43–1.55) GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from −94 dBc/Hz to −124 dBc/Hz @600 kHz offset from the carrier with an overall reduced amplitude noise for the VCO.     

超宽频带VHF频段CMOS LC VCO

实现了一个宽频带VHF频段CMOS VCO.其最大的改进在于将振荡器中交叉耦合MOS管分为并联可开关的若干段.这样使其特性可以在较大范围内补偿VCO调频过程中状态的变化.该VCO使用标准0.18μmCMOS工艺制作,核心版图面积约为550μm×700μm.测试结果表明:该VCO频率覆盖范围为31～111MHz;功耗为0.3～6.9mW;在100kHz频偏处相位噪声约-110dBc/Hz.     

Low-Phase Noise Hartley Differential CMOS Voltage Controlled Oscillator

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18-mum 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about -119dBc/Hz at 4.02GHz and 122dBc/Hz at 4.5GHz. The power consumption of the VCO core is 6.75mW     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO)with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between-118.5 dBc/Hz and-122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the mnmg range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.     

A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations

In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-mum CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of -118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and -114 dBc/Hz, respectively     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.