TDDB击穿特性评估薄介质层质量

与时间相关电介质击穿(TDDB)测量是评估厚度小于20nm薄栅介质层质量的重要方法.氧化层击穿前,隧穿电子和空穴在氧化层中或界面附近产生陷阱、界面态,当陷阱密度超过临界平均值 _bd时,发生击穿.击穿电量Q_bd值表征了介质层的质量.Q_bd值及其失效统计分布与测试电流密度、电场强度、温度及氧化层面积等有定量关系.TDDB的早期失效分布可以反映工艺引入的缺陷.TDDB可以直接评估氧化、氮化、清洗、刻蚀等工艺对厚度小于10nm的栅介质质量的影响.它是硅片级评估可靠性和预测EEPROM擦写次数的重要方法.     

薄SiO2层击穿特性与临界陷阱密度

薄栅氧化层的退化、击穿与氧化层中和界面陷阱的产生相关.本文研究了在恒电流TDDB(Time-Dependent Dielectric Breakdown) 应力条件下8.9nm薄氧化层的电学特性退化、击穿情况.研究表明,电子在穿越SiO₂晶格时与晶格相互作用产生陷阱,当陷阱密度达到某一临界密度N_bd时,氧化层就击穿.N_bd可以用来表征氧化层的质量,与测试电流密度无关.击穿电量Q_bd随测试电流密度增大而减小可用陷阱产生速率的增长解释.临界陷阱密度N_bd随测试MOS电容面积增大而减小,这与统计理论相符.统计分析表明,对于所研究的薄氧化层,可看作由面积为2.56×10^-14cm²的"元胞"构成,当个别"元胞"中陷阱数目达到13个时,电子可通过陷阱直接隧穿,"元胞"内电流突然增大,产生大量焦耳热,形成欧姆通道,氧化层击穿.     

含N超薄栅氧化层的击穿特性

研究了含N超薄栅氧化层的击穿特性.含N薄栅氧化层是先进行900C干氧氧化5min,再把SiO2栅介质放入1000C的N2O中退火20min而获得的,栅氧化层厚度为10nm.实验结果表明,在栅介质中引入适量的N可以明显地起到抑制栅介质击穿的作用.分析研究表明,N具有补偿SiO2中O3 Si@和Si3 Si@等由工艺引入的氧化物陷阱和界面陷阱的作用,从而可以减少初始固定正电荷和Si/SiO2界面态,因此提高了栅氧化层的抗击穿能力.     

3.4nm超薄SiO2栅介质的特性

用LOCOS工艺制备出栅介质厚度为3.4nm的MOS电容样品,通过对样品进行I-V特性和恒流应力下V-t特性的测试,分析用氮气稀释氧化法制备的栅介质的性能,同时考察了硼扩散对栅介质性能的影响.实验结果表明,制备出的3.4nm SiO₂栅介质的平均击穿场强为16.7MV/cm,在恒流应力下发生软击穿,平均击穿电荷为2.7C/cm².栅介质厚度相同的情况下,P⁺栅样品的击穿场强和软击穿电荷都低于N⁺栅样品.     

含N超薄栅氧化层的击穿特性

研究了含 N超薄栅氧化层的击穿特性 .含 N薄栅氧化层是先进行 90 0℃干氧氧化 5 m in,再把 Si O2 栅介质放入 10 0 0℃的 N2 O中退火 2 0 min而获得的 ,栅氧化层厚度为 10 nm.实验结果表明 ,在栅介质中引入适量的 N可以明显地起到抑制栅介质击穿的作用 .分析研究表明 ,N具有补偿 Si O2 中 O3≡ Si·和 Si3≡ Si·等由工艺引入的氧化物陷阱和界面陷阱的作用 ,从而可以减少初始固定正电荷和 Si/ Si O2 界面态 ,因此提高了栅氧化层的抗击穿能力     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

不同工艺超薄栅氧化层的抗击穿特性

对注F、注N以及先注N后注F超薄栅氧化层的击穿特性进行了实验研究,实验结果表明,在栅介质中引入适量的F或N都可以明显地提高栅介质的抗击穿能力.分析研究表明,栅氧化层的击穿主要是由于正电荷的积累造成的,F或N的引入可以补偿Si/SiO2界面和SiO2中的O3≡Si·和Si3≡Si·等由工艺引入的氧化物陷阱和界面陷阱,从而减少了初始固定正电荷和Si/SiO2界面态,提高了栅氧化层的质量.通过比较发现,注N栅氧化层的抗击穿能力比注F栅氧化层强.     

超薄Si3N4/SiO2叠层栅介质可靠性研究

实验成功地制备出等效氧化层厚度为亚2nm的Nitride/Oxynitride(N/O)叠层栅介质难熔金属栅电极PMOS电容并对其进行了可靠性研究.实验结果表明相对于纯氧栅介质而言,N/O叠层栅介质具有更好的抗击穿特性,应力诱生漏电特性以及TDDB特性.进一步研究发现具有更薄EOT的难熔金属栅电极PMOS电容在TDDB特性以及寿命等方面均优于多晶硅栅电极的相应结构.     

栅介质氧化层缺失缺陷的形成原因及解决方案

氮氧化技术是45 nm及以下技术节点栅介质制备的关键工艺,严格控制由氮氧化工艺所诱发的界面缺陷是提高栅介质质量的重点.研究了形成栅介质氧化层缺失缺陷的原因,并提出了解决方案.结果表明,原位水蒸气生成(ISSG)热氧化形成栅介质氧化层后的实时高温纯惰性氮化热处理工艺是形成栅介质氧化层缺失缺陷的主要原因;在实时高温纯惰性氮化热处理工艺中引入适量的O2,可以消除栅介质氧化层的缺失缺陷.数据表明,引入适量O2后,栅介质氧化层的界面陷阱密度(Dit)和界面总电荷密度(ΔQtot)分别减少了12.5％和26.1％;pMOS器件负偏压不稳定性(NBTI)测试中0.1％样品失效时间(t0.1％)和50％样品失效时间(t50％)分别提高了18％和39％;32 MB静态随机存储器(SRAM)在正常工作电压和最小工作电压分别提高了9％和13％左右.     

薄栅氧化层相关击穿电荷

栅氧化层厚度的减薄要求深入研究薄栅介质的击穿和退化之间的关系 .利用衬底热空穴注入技术分别控制注入到薄栅氧化层中的热电子和空穴量 ,对相关击穿电荷进行了测试和研究 .结果表明薄栅氧化层击穿的限制因素依赖于注入热电子量和空穴量的平衡 .提出薄栅氧化层的击穿是在注入的热电子和空穴的共同作用下发生的新观点 .建立了 Si O2 介质击穿的物理模型并给出了理论分析     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

Oxide reliability: influence of interface roughness, structure layout, and depletion layer formation

The charge to breakdown Q_bd and the breakdown voltage V_bd distributions obtained on 7.5 and 12 nm thick gate oxides (GOX) using two different wafer level reliability current ramp algorithms are discussed in terms of the GOX interface roughness and the depletion effects during the stress. The observed influence of the interface roughness on the GOX properties seems to be very sensitive to the gate polarity during the stress or the injection direction of electrons. Especially the roughness of the interface through which electrons are injected into the gate oxide influences the oxide reliability. The effect of the interface roughness turned out to depend strongly on the test acceleration level. A possibility of masking of the roughness (reduction of the “effective roughness”) of the GOX/Si interface as a result of strong depletion at higher accelerations is discussed.     

Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N₂O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N₂O nitridation piles up in the oxide at the Si–SiO₂ interface regardless of nitridation time. The results obtained show improved breakdown field (E_bd), and charge-to-breakdown (Q_bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density (D_it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Charge trapping and reliability characteristics of ultra-thin HfYOx films on n-GaAs substrates

Ultra-thin layers of the HfYO_x gate dielectric were deposited on n-GaAs substrates by employing radio frequency (rf) sputter deposition system with a Si interface control layer sandwiched between the dielectric and semiconductor. The trapping/detrapping behaviour of charge carriers in the ultra-thin HfYO_x/Si gate dielectric stack has been extensively studied during constant-voltage stressing (CVS) and compared with the results obtained from directly deposited HfYO_x films on n-GaAs. The increase in gate leakage current observed during electrical stress is estimated and explained by taking into account the build up of trap charges and stress induced trap generation. Also, the capture cross-section of the generated traps is estimated. The variation of the trap centroid and the trapped charge density with injected influences have been investigated using constant current stressing (CCS) measurements. The dielectric breakdown and reliability of the dielectric films have been studied using constant-voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd  1700 s) is observed for HfYO_x gate dielectric with a silicon inter-layer under a high constant-voltage stress (8 V).     

Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device

The electrical properties of HfO₂ gate dielectric as a MOS structure deposited using Dense Plasma Focus (DPF) device under different ambient gases were investigated. DPF is unique machine used for the first time to fabricate a MOS device as it can be used to deposit dielectric film in one shot and can also be used to change the properties of the thin film surface. The films were first deposited under pre-optimized conditions of DPF device to have best focus for producing ions. The substrate for deposition of dielectric material was placed at a distance of 5 cm from the focus under argon ambient and then under nitrogen ambient. The I-V, C-V characteristics of the dielectric film were investigated employing Al-HfO₂-Si MOS capacitor structure deposited using DPF. The MOS devices were studied to determine electrical parameters like breakdown voltage, oxide charges and leakage current deposited under two different gas ambient. The microstructure of thin film is examined by using AFM and the thickness of the film is examined using an ellipsometer. The reduction in surface roughness, shift in Flat-band voltage (V_fb) and reduction in oxide-charge density (Q_ox) is seen maximum for MOS capacitor where HfO₂ as gate dielectric is deposited under nitrogen ambient using DPF machine.     

Dielectric breakdown characteristics and interface trapping of hafnium oxide films

The reliability and integrity of HfO₂ prepared by direct sputtering of hafnium were studied. By monitoring the current-voltage and current-stressing duration characteristics, we found a significant charge trapping effect in thin film with very short stressing time (<30 s) but the stress-induced trap generation is insignificant. The breakdown characteristics of hafnium gate oxide were also investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown were observed. Results suggest that the soft and hard breakdowns should have different precursor defects. A two-layer breakdown model of is proposed to explain these observations.     

Highly robust ultrathin silicon nitride films grown atlow-temperature by microwave-excitation high-density plasma for gigascale integration

This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400°C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation