Ku波段GaAs微波单片集成电路

本文介绍Ku波段GaAs单片集成电路的设计、研制和测量结果。该单片电路的匹配网络采用对FET进行计算机分析和电路模拟相结合的方法进行设计。研制成功了一个两级单片电路,其尺寸为1.9×3.2×0.1mm,在14.5～15.4GHz的频率范围内,输出功率P_0≥100mW,增益G_P≥5dB,带内增益起伏△G_P≤±0.75dB。     

A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

10 Gbit/s low-power bit synchroniser with automatic retiming phase alignment

A 10 Gbit/s bit-synchroniser circuit has been fabricated using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. The differential gain of the exclusive-or phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/+21 degrees relative to the 'in bit cell centre' position of the negative going clock edge. The chip has a power dissipation of 160 mW when using a supply voltage of 1.90 V.<>     

一种基于0.35 μm CMOS工艺的单片集成微机械陀螺仪接口电路

本文介绍了一种用于读取角速度信号的单片集成微机械陀螺仪接口电路,该接口电路采用了相关双采样技术以抑制1/f噪声和运算跨导放大器的失调.为了方便系统仿真和测试,本文设计了一种微机械陀螺仪的等效电路.该接口电路采用0.35 μm CMOS工艺设计并制造,芯片总面积为1.09mm×0.87mm.后仿真结果表明,该接口电路能达到0.58aF的电容分辨精度,动态范围达99.7dB.测试结果表明,接口电路系统增益为26.6mV/fF,在3.5V电源电压下系统总功耗为20.4mW.     

基于GaAs PHEMT的Ku波段宽带单片中功率放大器

设计并实现了一款Ku波段宽带单片中功率放大器,依据电路原理设计了功率放大器电路,利用ADS软件对设计的电路和版图分别进行了电学参数优化与电磁仿真.放大器采用0.25 μm栅长的GaAs PHEMT作为有源器件,芯片衬底减薄至80μm,采用了NiCr金属膜电阻、重叠式MIM(金属-绝缘体-金属)电容器、空气桥连接和背面通...     

Ultra-High-Speed GaAs Monolithic Prescaler and Phase Frequency Comparator IC

A high-speed, low-power prescaler and phase frequency comparator (PFC) IC for a phase-lock stable oscillator was designed and fabricated on a single chip using GaAs MESFET BFL circuitry. The gate width of the master-slave T-type flip-flops used in designing the 1/32 frequency divider prescaler was determined by circuit simulations. The fabricated 1/32 prescaler operated up to 8.0 GHz while the fabricated monolithic prescaler and PFC IC performed stable division, and phase and frequency comparison at input frequencies up to 4.8 GHz with a chip power dissipation of only 715 mW.     

High linearity 5.2-GHz power amplifier MMIC using CPW structure technology with a linearizer circuit

A built-in linearizer was applied to improve the linearity in a 5.2-GHz power amplifier microwave monolithic integrated circuit (MMIC), which was undertaken with 0.15-μm AlGaAs/InGaAs D-mode PHEMT technology.The power amplifier (PA) was studied taking into account the linearizer circuit and the coplanar waveguide (CPW) structures. Based on these technologies, the power amplifier, which has a chip size of 1.44 × 1.10 mm~2, obtained an output power of 13.3 dBm and a power gain of 14 dB in the saturation region. An input third-order intercept point (IIP_3) of-3 dBm, an output third-order intercept point (OIP_3) of 21.1 dBm and a power added efficiency (PAE) of 22% were attained, respectively. Finally, the overall power characterization exhibited high gain and high linearity, which illustrates that the power amplifier has a compact circuit size and exhibits favorable RF characteristics. This power circuit demonstrated high RF characterization and could be used for microwave power circuit applications at 5.2 GHz.     

A 2.5-GHz InGaP/GaAs differential cross-coupled self-oscillating mixer (SOM) IC

This letter presents a monolithic differential cross-coupled self-oscillating mixer (SOM). The SOM chip is fabricated using an InGaP/GaAs heterojunction bipolar transistor (HBT) foundry process and operates at 2.5 GHz. The chip provides voltage controlled oscillator (VCO) operation, up- and down-conversion mixing, and injection locking functionalities. The voltage down-conversion gain and the power up-conversion gain of up to 15 and 11.5 dB, respectively, are measured for the circuit. There is a compromise between obtaining a high conversion gain, and the oscillator power (-0.3 dBm for a 5-V supply) and phase noise (-84 dBc/Hz at 100 kHz). However, phase noise improvement of 32dB is observed by injection of a -30-dBm stable reference.     

A fully integrated V-band PLL MMIC using 0.15-/spl mu/m GaAs pHEMT technology

A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-/spl mu/m GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35/spl times/1.80 mm/sup 2/. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip.     

5~6GHz自适应线性化偏置的InGaP/GaAs HBT功率放大器

针对高质量无线局域网的传输需求,设计了一款工作在5~6 GHz的宽带磷化镓铟/砷化镓异质结双极型晶体管(InGaP/GaAs HBT)功率放大器芯片。针对HBT晶体管自热效应产生的非线性和电流不稳定现象,采用自适应线性化偏置技术,有效地解决了上述问题。针对射频系统的功耗问题,设计了改进的射频功率检测电路,以实现射频系统的自动增益控制,降低功耗。通过InGaP/GaAs HBT单片微波集成电路(MMIC)技术实现该功率放大器芯片。仿真结果表明,功放芯片的小信号增益达到32 dB;1 dB压缩点功率为28.5 dBm@5.5 GHz,功率附加效率PAE超过32%@5.5 GHz;输出功率为20 dBm时,IMD3低于-32 dBc。     

1.25 Gbit/s光接收机限幅放大器

文章介绍了采用0.35 μm双极型互补氧化物半导体(BiCMOS)工艺制作的光纤通信用低功耗的1.25 Gbit/s限幅放大器,其电路采用3.3 V单电源供电,电路增益可以达到70 dB,功耗为20 mW,在27 dB的输入动态范围内,可以保持800 mV的恒定输出摆幅.整个芯片的面积为1.30 mm×0.75 mm.     

A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

A five-terminal plus or minus 15-V monolithic voltage regulator

A five-terminal /spl plusmn/15-V monolithic voltage regulator has been developed that incorporates internal frequency compensation and internally provides a /spl plusmn/1 percent output voltage tolerance. In addition, a thermally symmetric layout design of the chip has been used to eliminate the detrimental effects of thermal feedback on the die and ensure that the complementary tracking output voltages will be independent of the power dissipation in the series pass power transistors. Complete fault protection is accomplished by providing the power transistors with good dc safe operating area, internally limiting the short circuit output currents, and accurately limiting the junction temperature to within 10/spl deg/C of the specified maximum limit. Also, a new Zener diode geometry is employed that significantly reduces the noise associated with the reference voltage.     

Low-Noise, Low Power Dissipation GaAs Monolithic Broad-Band Amplifiers

Low-noise, low dc power dissipation GaAs monolithic amplifiers have been developed for use in VHF-UHF mobile radio systems. The developed amplifiers have two-stage constuction, where gate width for the first stage is 1000 µm, and for the second stage is 500 pm. Using this circuit configuration, both noise figure and bandwidth have been improved. To maintain the uniformity for the ion-implanted active layers and to reduce gate-source resistance R/sub S/ and gate-drain resistance R/sub D/, the "closely spaced electrode FET" was adopted. The FET enables low drain voltage operation, resulting in low dc power dissipation. The developed amplifier for the FET threshold voltage VT= --0.6 V provides a 3-dB noise figure, less than 170-mW dc power dissipation, 9-MHz-3.9-GHz bandwidth with 16-dB gain. It can operate under a unipolar power source. When external choke inductors were introduced for the amplifier, 120-mW dc power dissipation has been achieved. It has also been demonstrated that the amplifier for V/sub T/= --0.6V, which is inferior to the amplifier for VT= -2.7V regarding gain-bandwidth product and power efficiency under the same dc power dissipation, however, has an acceptable performance for use in the mobile radio systems.     

采用电流复用拓扑的宽带收发一体多功能电路

基于标准的GaAs赝配高电子迁移率晶体管(PHEMT)单片微波集成电路(MMIC)工艺设计并制备了一款宽带收发一体多功能电路芯片.该多功能芯片包含了功率放大器、低噪声放大器和收发开关.放大器采用电流复用拓扑结构实现了低功耗的目标.收发开关采用浮地结构避免了使用负电源.芯片在14～ 24 GHz工作频率的实测结果显示:接收支路噪声系数小于3.0dB,增益大于18 dB,输入及输出电压驻波比(VSWR)均小于2.0,1 dB压缩点输出功率大于0 dBm,直流功耗为60 mW;发射支路增益大于21 dB,输入输出VSWR均小于1.8,1dB压缩点输出功率大于10 dBm,直流功耗为180 mW.芯片尺寸为2 600 μm×1 800 μm.该多功能收发电路的在片测试结果和仿真结果一致,性能达到了设计要求.     

Linearised InGaP/GaAs HBT MMIC power amplifier with active biascircuit for W-CDMA application

A high linearity InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) power amplifier is demonstrated using a new structure for a bias circuit for wideband-code division multiple access (W-CDMA) application. A one shunt capacitor is added to a novel active bias circuit and acts as a lineariser improving input P_{1 dB} of 16 dB and phase distortion of 5.1° for the hybrid phase shift keying (HPSK) modulated signal at the 28 dBm output power; the lineariser showing no significant increase of signal loss and chip area. The two-stage HBT MMIC amplifier exhibits a power-added efficiency (PAE) of 37%, a linear power gain of 24.5 dB, and an output power of 28 dBm with an adjacent channel power ratio (ACPR) of -45 dBc, under a 3 V operation voltage     

A unique MMIC broadband power amplifier approach

A broadband monolithic microwave integrated circuit (MMIC) power amplifier design approach is described using lossy matching networks in the form of a bridged-T all-pass network. This approach offers the advantage of exceptional gain flatness, good input VSWR, high efficiency, and small size. A two-stage amplifier is described that delivers power greater than 1 W across the 2 to 6-GHz range with a linear gain of 20 dB, an input VSWR better than 1.7:1, and a power-added efficiency of 30% to 37% with a chip area less than 4.4 mm²     

2~26GHzGaAs单片功率放大器

报道了一个具有低噪声性能的2~26GHz GaAs超宽带单片功率放大器的研究结果,介绍了模型提取、电路设计和单片制作的全过程.放大器采用分布式设计,在超宽带频率范围内增益为6.5±0.5dB,输入输出驻波比小于2.0.在2~20GHz内测得输出功率大于300mW,噪声系数为3.5~5.5dB.单片放大器包括所有匹配、隔直及偏置电路,芯片面积为3.2mm×1.275mm×0.1mm.     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

10 GB/s bit-synchronizer circuit with automatic timing alignment byclock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V