声表面波大带宽滤波器的设计

报道在Ｙ旋１２７．８６°Ｘ传ＬｉＮｂＯ＿３基片上采用１／８λ＿０，５／８λ＿０结构的切指加权换能器的声表面波滤波器，成功地研制了中心频率为４０ＭＨｚ，３ｄＢ带宽为２０ＭＨｚ，矩形系数（Δｆ＿４０ｄＢ／Δｆ＿３ｄＢ）为１．４８，带内波动＜１．２ｄＢ，带外抑制＞４０ｄＢ．插入损耗＜３８ｄＢ，相对带宽（Δｆ＿－３ｄＢ／ｆ＿０）大于５０％的滤波器。     

用于脉冲压缩雷达的声表面波部件

介绍一种用于脉冲压缩雷达的声表面波部件。它包含了声表面波脉压线、声表面波振荡器和重要的电子线路。该部件产生一种脉冲展宽信号，其工作频率为９６０ＭＨｚ，信号带宽为６ＭＨｚ，色散时间为１０μｓ，杂波电平≤－５０ｄＢｃ。专门设置的９００ＭＨｚ本振输出电平≥７ｄＢｍ，杂散电平≤－８０ｄＢｃ     

一种宽带低损耗表面波滤波器

阐述了一种利用纵向耦合双模制作宽带损耗声表面波滤波器方法，给出了理论计算方法和计算机模拟结果，最后给出制作中心频率为４５３ＭＨｚ的声表面波滤波器实验结果，插入损耗为１．９ｄＢ，１ｄＢ带宽为６．６６ＭＨｚ远端带外抑制大于４５ｄＢ。     

一种宽带低损耗声表面波滤波器

阐述了一种利用纵向耦合双模制作宽带低损耗声表面波滤波器的方法，给出了理论计算方法和计算机模拟结果，最后给出了制作中心频率为４５３ＭＨｚ的声表面波滤波器实验结果，插入损耗为１．９ｄＢ，１ｄＢ带宽为６．６６ＭＨｚ，远端带外抑制大于４５ｄＢ。     

顶部超平SAW滤波器的研制及其在频率捷变模拟系统的应用：频率捷变信 …

频率范围在１０ＭＨｚ至３ＧＨｚ快速捷变信号的研制基于对１４－５８ＭＨｚ的信号的直接数字合成。在基带信号转化为中心频率为３０４ＭＨｚ，利用已实现的高性能声表面波滤波器来提高ＩＦ滤波。４４ＭＨｚ宽滤波器典型的能带波纹小于０．４ｄＢ（峰对峰），三次行程，电磁耦合和其它乱真信号被抑制为５０ｄＢ，电路，ＳＡＷ滤波器及其封装被精心设计成能够得到这种特性。     

声表面波VCO的研制

介绍了１５５．５２ＭＨｚ、６２２．０８ＭＨｚ声表面波（ＳＡＷ）、１２４４．１６ＭＨｚ浅体波（ＳＴＷ）压控振荡器（ＶＣＯ）的原理、设计和性能。采用低插损、高Ｑ值的ＳＡＷ延迟线和ＳＴＷ谐振器，高性能微波放大器，变容二极管电移相器，使振荡器具有非常低的相位噪声（＜－１４０ｄＢｃ／Ｈｚａｔ１００ｋＨｚ）、高输出功率（＞９ｄＢｍ）、低温度－频率漂移（＜±３５ｐｐｍ，温度范围：－５～６０℃）、大频率调谐范围（＞４００ｐｐｍ）。     

混合集成低噪声宽带AGC放大器

采用厚膜混合集成工艺，研制出ＳＨ３０９－１低噪声宽带ＡＧＣ放大器，其噪声系数≤１．５ｄＢ，最大输入电平≥４００ｍＶ／５００Ω，增益≥５０ｄＢ，增益控制范围≥５０ｄＢ，工作频率范围为６０ＭＨｚ±１０ＭＨｚ。主要介绍了其设计原理及应用。     

高性能PCS双工器

Ｋ&ＬＭｉｃｒｏｗａｖｅ推出了ＷＳＤ-００１３２／００１３３／００１３４型高性能ＰＣＳ双工器。这三种型号的接收频段分别为１８５０～１８７０ＭＨｚ、１８７０～１８９０ＭＨｚ和１８９０～１９１０ＭＨｚ,它们的发射频段分别为１９３０～１９５０ＭＨｚ、１９５０～１９７０ＭＨｚ和１９７０～１９９０ＭＨｚ。接收带内的插入损耗小于１．５ｄＢ,发射带内的插入损耗小于０．９ｄＢ;所有带内的回波损耗最小为１４ｄＢ,可额定发射１０ＷＣＷ和１００ＷＰＩＰ（瞬时功率）。工作温度范围为０～５０℃,大小为１０６．７ｍｍ×６３．５ｍ…     

实用资料

飞利浦CATV放大模块一览表型号(ＭＨｚ)增益(ｄＢ)斜率(ｄＢ)平坦度(ｄＢ)最大值反射损耗 (输入/输出 )(ｄＢ)最小值三阶组合差拍(ｄＢ)最大值交扰调制(ｄＢ)最大值二级组合差拍(ｄＢ)最大值二阶差拍(ｄＢ)最大值输出电平(ｄＢｍＶ)最小值噪声系数(ｄＢ)最大值总ＤＣ电流消耗(ｍＡ)最大值5-75　反向放大器ＢＧＹ68@1 0ＭＨｚ3 0± 0 .8--0 .2～ 0 .5± 0 .2 2 04频道-684频道-60 --702 5ＭＨｚ5.0 1 3 55-1 2 0反向放大器ＢＧＹ66Ｂ@1 0ＭＨｚ2 5± 0 .5--0 .2～ 0 .5± 0 .2 2 01 4频道-661 4频道-54--70 60 .0@1 2 0ＭＨｚ5.0 1 3 55-2 …     

无绳电话用声表面波滤波器

本文讨论了研制的两种无绳电话机用声表面波滤波器，中心频率为４６．５７ＭＨｚ和４９．９ＭＨｚ；△ｆ＿（－３ｄＢ）＝１．７ＭＨＺ；插损≤１０ｄＢ；△ｆ＿（－４０ｄＢ）／△ｆ＿（－３ｄＢ）≤３．５；阻带抑制≤－４０ｄＢ。采用了低插损的三换能器结构。输入叉指换能器采用了波阵面均匀的孔径加权和相位加权，减小了变迹损耗。理论计算与实验结果一致。     

10‐Bit 200‐MS/s Current‐Steering DAC Using Data‐Dependant Current‐Cell Clock‐Gating

This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with V_DD=1.2 V. Its area is 0.21 mm². It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively.     

A broadband circularly polarized antenna of square-ring patch for UHF RFID reader applications

A circularly polarized, broad bandwidth, square-ring patch antenna for radio-frequency identification (RFID) is proposed. The antenna has a dimension of 100 × 100 × 22.9 mm³. By using a Wilkinson power divider and a patch-antenna structure, a measured 3-dB axial-ratio bandwidth of approximately 140 MHz (16.47%), an impedance bandwidth of 136 MHz (15.81%), and a measured peak gain of approximately 6.8 dBic are being achieved. The operating band of the proposed antenna is suitable for China (840–846 MHz), Europe (865–868 MHz) and the United States (902–928 MHz) ultra-high frequency (UHF) RFID applications.     

带有输入、输出滤波器的前置放大器

叙述了一种带有输入、输出滤波器的前置放大器的设计。在该滤波放大组件的设计中,主要解决了低插损、高隔离、小型化同轴滤波器和高增益、低噪声、温度性能稳定的放大器的优化设计,理论计算与实验结果相符合。主要研制结果:f_0=1 575.42MHz,G>39dB,NF<1.6dB,△f_(3dB)<30MHz,f_(30dB)<100MHz,f_(50dB)<200MHz。     

Design and performance of compact low noise GaAs MESFET amplifiers for UHF operation

The design considerations and experimental results of compact low noise GaAs MESFET Amplifiers for UHF operation are described in this paper. The miniaturized and optimized circuits are obtained by means of special matching network and CAD technique. Both a two-stage unit at 700 MHz and a three-stage unit at 1000 MHz are fabricated on a 50×60 mm² alumina substrate, and power gain of 29 dB and 30 dB, noise figure of 0.8 and 1.2 dB and bandwidth of 40 MHz (3 dB) and 100 MHz (1 dB) are obtained respectively. The satellite direct broadcasting TV receiver fabricated with a 700 MHz GaAs MESFET amplifier has clear pictures and good sound.     

Ku波段宽带机调耿氏振荡器

本文介绍了Ku波段宽带机械调谐耿氏振荡器的实用电路结构、设计原则以及运用双金属补偿技术得到的实验结果。振荡器输出功率为50120mW;机调范围一般为10001500MHz,最宽优于2500MHz;频率温度系数一般小于0.07MHz/℃,最低优于0.01MHz/℃;功率温度系数一般小于0.015dB/℃,最低优于0.007dB/℃。     

A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency

In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 × 0.65 mm².     

TD-SCDMA A频段交叉耦合腔体滤波器的设计与实现

TD-SCDMA采用的是TDD工作方式,收发采用相同的频带,由于PHS的存在,A频段带宽为1 8801 900 MHz,体积有严格要求110 mm×75 mm×30 mm,难点是在此体积下实现带内最大插损小于0.9 dB,插损纹波小于等于士0.3 dB,回波损耗大于18 dB的设计要求,带外抑制要求S<,21><-75...     

Asymmetric and symmetric modified bow-tie slotted circular patch antennas for circular polarization

Modern communication systems employ wideband antennas with circular polarization (CP) radiation. In this work, asymmetric modified bow-tie (ABT) and symmetric modified bow-tie (SBT) slotted circularly polarized single-point probe-fed circular patch antennas with dimensions of 40 mm × 40 mm for wideband applications are proposed. A 10 dB RL bandwidth of 350 MHz with CP, 3 dB axial ratio (AR) bandwidth of 100 MHz, peak gain of 4.9 dBic, and 10 dB RL bandwidth of 530 MHz with CP, 3 dB AR bandwidth of 140 MHz, peak gain of 5 dBic are obtained for ABT and SBT slotted circular patch antennas, respectively. The proposed SBT slotted patch is scaled up and down to 50 mm × 50 mm and 30 mm × 30 mm, respectively. The proposed scaled-up version offers 10 dB RL and 3 dB AR bandwidths of 340 MHz and 80 MHz, with a peak gain of 5 dBic. The scaled-down version offers 10 dB RL and 3 dB AR bandwidths of 710 MHz and 180 MHz, with a peak gain of 5.25 dBic. These prototypes are suitable to work in IEEE 802.11a WLAN, ISM, and IEEE 802.11ac applications. The measured and simulated results are then discussed and compared.     

A low voltage SRAM for embedded applications

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 μW. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 μW. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power     

Third order lowpass Butterworth filter function realisation using CFA

A new realisation scheme for third order lowpass Butterworth filter function (BFF) using two CFA devices and few RC components is presented. The design equations utilise the transadmittance elements of the devices. The maximally flat response at select frequencies in the range 5 MHz ≤ f _o ≤ 30 MHz had been verified with PSPICE macromodel simulation and by hardware circuit implementation using the AD-844 device. The active sensitivities are quite low. The simulation result and the measured responses are included for f _o = 5.1 MHz and 22.2 MHz.