共查询到20条相似文献,搜索用时 78 毫秒
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报道在Y旋127.86°X传LiNbO_3基片上采用1/8λ_0,5/8λ_0结构的切指加权换能器的声表面波滤波器,成功地研制了中心频率为40MHz,3dB带宽为20MHz,矩形系数(Δf_40dB/Δf_3dB)为1.48,带内波动<1.2dB,带外抑制>40dB.插入损耗<38dB,相对带宽(Δf_-3dB/f_0)大于50%的滤波器。 相似文献
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用于脉冲压缩雷达的声表面波部件 总被引:1,自引:0,他引:1
介绍一种用于脉冲压缩雷达的声表面波部件。它包含了声表面波脉压线、声表面波振荡器和重要的电子线路。该部件产生一种脉冲展宽信号,其工作频率为960MHz,信号带宽为6MHz,色散时间为10μs,杂波电平≤-50dBc。专门设置的900MHz本振输出电平≥7dBm,杂散电平≤-80dBc 相似文献
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一种宽带低损耗表面波滤波器 总被引:2,自引:2,他引:0
阐述了一种利用纵向耦合双模制作宽带损耗声表面波滤波器方法,给出了理论计算方法和计算机模拟结果,最后给出制作中心频率为453MHz的声表面波滤波器实验结果,插入损耗为1.9dB,1dB带宽为6.66MHz远端带外抑制大于45dB。 相似文献
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频率范围在10MHz至3GHz快速捷变信号的研制基于对14-58MHz的信号的直接数字合成。在基带信号转化为中心频率为304MHz,利用已实现的高性能声表面波滤波器来提高IF滤波。44MHz宽滤波器典型的能带波纹小于0.4dB(峰对峰),三次行程,电磁耦合和其它乱真信号被抑制为50dB,电路,SAW滤波器及其封装被精心设计成能够得到这种特性。 相似文献
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采用厚膜混合集成工艺,研制出SH309-1低噪声宽带AGC放大器,其噪声系数≤1.5dB,最大输入电平≥400mV/500Ω,增益≥50dB,增益控制范围≥50dB,工作频率范围为60MHz±10MHz。主要介绍了其设计原理及应用。 相似文献
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《国外电子元器件》2001,(3)
飞利浦CATV放大模块一览表型号(MHz)增益(dB)斜率(dB)平坦度(dB)最大值反射损耗 (输入/输出 )(dB)最小值三阶组合差拍(dB)最大值交扰调制(dB)最大值二级组合差拍(dB)最大值二阶差拍(dB)最大值输出电平(dBmV)最小值噪声系数(dB)最大值总DC电流消耗(mA)最大值5-75 反向放大器BGY68@1 0MHz3 0± 0 .8--0 .2~ 0 .5± 0 .2 2 04频道-684频道-60 --702 5MHz5.0 1 3 55-1 2 0反向放大器BGY66B@1 0MHz2 5± 0 .5--0 .2~ 0 .5± 0 .2 2 01 4频道-661 4频道-54--70 60 .0@1 2 0MHz5.0 1 3 55-2 … 相似文献
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本文讨论了研制的两种无绳电话机用声表面波滤波器,中心频率为46.57MHz和49.9MHz;△f_(-3dB)=1.7MHZ;插损≤10dB;△f_(-40dB)/△f_(-3dB)≤3.5;阻带抑制≤-40dB。采用了低插损的三换能器结构。输入叉指换能器采用了波阵面均匀的孔径加权和相位加权,减小了变迹损耗。理论计算与实验结果一致。 相似文献
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This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with VDD=1.2 V. Its area is 0.21 mm2. It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively. 相似文献
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带有输入、输出滤波器的前置放大器 总被引:1,自引:1,他引:0
叙述了一种带有输入、输出滤波器的前置放大器的设计。在该滤波放大组件的设计中,主要解决了低插损、高隔离、小型化同轴滤波器和高增益、低噪声、温度性能稳定的放大器的优化设计,理论计算与实验结果相符合。主要研制结果:f_0=1 575.42MHz,G>39dB,NF<1.6dB,△f_(3dB)<30MHz,f_(30dB)<100MHz,f_(50dB)<200MHz。 相似文献
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A circularly polarized, broad bandwidth, square-ring patch antenna for radio-frequency identification (RFID) is proposed. The antenna has a dimension of 100 × 100 × 22.9 mm3. By using a Wilkinson power divider and a patch-antenna structure, a measured 3-dB axial-ratio bandwidth of approximately 140 MHz (16.47%), an impedance bandwidth of 136 MHz (15.81%), and a measured peak gain of approximately 6.8 dBic are being achieved. The operating band of the proposed antenna is suitable for China (840–846 MHz), Europe (865–868 MHz) and the United States (902–928 MHz) ultra-high frequency (UHF) RFID applications. 相似文献
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The design considerations and experimental results of compact low noise GaAs MESFET Amplifiers for UHF operation are described
in this paper. The miniaturized and optimized circuits are obtained by means of special matching network and CAD technique.
Both a two-stage unit at 700 MHz and a three-stage unit at 1000 MHz are fabricated on a 50×60 mm2 alumina substrate, and power gain of 29 dB and 30 dB, noise figure of 0.8 and 1.2 dB and bandwidth of 40 MHz (3 dB) and 100
MHz (1 dB) are obtained respectively. The satellite direct broadcasting TV receiver fabricated with a 700 MHz GaAs MESFET
amplifier has clear pictures and good sound. 相似文献
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Piero Malcovati Luca Picolli Lorenzo Crespi Faouzi Chaahoub Andrea Baschirotto 《Analog Integrated Circuits and Signal Processing》2010,64(2):159-172
In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating
modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering
a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25
× 0.65 mm2. 相似文献
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TD-SCDMA A频段交叉耦合腔体滤波器的设计与实现 总被引:1,自引:0,他引:1
TD-SCDMA采用的是TDD工作方式,收发采用相同的频带,由于PHS的存在,A频段带宽为1 8801 900 MHz,体积有严格要求110 mm×75 mm×30 mm,难点是在此体积下实现带内最大插损小于0.9 dB,插损纹波小于等于士0.3 dB,回波损耗大于18 dB的设计要求,带外抑制要求S<,21><-75... 相似文献
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Modern communication systems employ wideband antennas with circular polarization (CP) radiation. In this work, asymmetric modified bow-tie (ABT) and symmetric modified bow-tie (SBT) slotted circularly polarized single-point probe-fed circular patch antennas with dimensions of 40 mm × 40 mm for wideband applications are proposed. A 10 dB RL bandwidth of 350 MHz with CP, 3 dB axial ratio (AR) bandwidth of 100 MHz, peak gain of 4.9 dBic, and 10 dB RL bandwidth of 530 MHz with CP, 3 dB AR bandwidth of 140 MHz, peak gain of 5 dBic are obtained for ABT and SBT slotted circular patch antennas, respectively. The proposed SBT slotted patch is scaled up and down to 50 mm × 50 mm and 30 mm × 30 mm, respectively. The proposed scaled-up version offers 10 dB RL and 3 dB AR bandwidths of 340 MHz and 80 MHz, with a peak gain of 5 dBic. The scaled-down version offers 10 dB RL and 3 dB AR bandwidths of 710 MHz and 180 MHz, with a peak gain of 5.25 dBic. These prototypes are suitable to work in IEEE 802.11a WLAN, ISM, and IEEE 802.11ac applications. The measured and simulated results are then discussed and compared. 相似文献
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A new realisation scheme for third order lowpass Butterworth filter function (BFF) using two CFA devices and few RC components is presented. The design equations utilise the transadmittance elements of the devices. The maximally flat response at select frequencies in the range 5 MHz ≤ f o ≤ 30 MHz had been verified with PSPICE macromodel simulation and by hardware circuit implementation using the AD-844 device. The active sensitivities are quite low. The simulation result and the measured responses are included for f o = 5.1 MHz and 22.2 MHz. 相似文献
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A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 μW. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 μW. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power 相似文献