Developing platform specific model for MPSoC architecture from UML-based embedded software models

In this paper, we describe a technique to design UML-based software models for MPSoC architecture, which focuses on the development of the platform specific model of embedded software. To develop the platform specific model, we define a process for the design of UML-based software model and suggest an algorithm with precise actions to map the model to MPSoC architecture. In order to support our design process, we implemented our approach in an integrated tool. Using the tool, we applied our design technique to a target system. We believe that our technique provides several benefits such as improving parallelism of tasks and fast-and-valid mapping of software models to hardware architecture.     

DSP外部Flash存储器的自烧写方式研究

阐述了Flash存储器在线编程的自烧写程序设计思想.被烧写目标文件作为数据嵌入到烧写程序中,经过编译链接生成最终的执行文件.运行烧写执行文件时,执行文件时将嵌入的目标数据烧写到Flash存储器中,从而实现在线或在系统编程.给出了相关程序的核心代码,并测试通过,可作为DSP嵌入式系统设计的参考.     

Linked Block-based Multiversion B-Tree index for PCM-based embedded databases

In this paper, by exploring the application characteristics of cyber-physical systems (CPS) and the performance characteristics of PCM, we propose a new B-tree index structure, called Linked Block-based Multi-Version B-Tree (LBMVBT), for indexing multi-version data in an embedded multi-version database for CPS. In LBMVBT, to reduce the number of writes to PCM in maintaining the index and improve the efficiency in serving version-range queries, we introduce the block-based scheme for indexing in which multiple versions of a data item are grouped into a version block to be indexed by a single entry in the multi-version index. To reduce the index re-organization cost (i.e., number of writes to PCM) due to node overflow and underflow, we add external entries in each index leaf node so that a node re-organization can be done by only updating pointers without copying the index entries of the re-organized leaf nodes to the new node. Analytic studies have been performed on LBMVBT and a series of experiments has been conducted to evaluate the efficacy of LBMVBT. The experimental results show that LBMVBT can effectively reduce the number of writes to the index and achieve a good overall performance on serving update transactions while version-range queries can be served with smaller number of reads to the index compared with MVBT.     

A Computation+Communication Load Balanced Loop Partitioning Method for Distributed Memory Systems

Due to a significant communication overhead of sending and receiving data, the loop partitioning approaches on distributed memory systems must guarantee not just the computation load balance but computation+communication load balance. The previous approaches in loop partitioning have achieved a communication-free, computation load balanced iteration space partitioning solution for a limited subset of DOALL loops. But a large category of DOALL loops inevitably result in communication and the trade-offs between computation and communication must be carefully analyzed for these loops in order to balance out the combined computation time and communication overheads. In this work, we describe a partitioning approach based on the above motivation for the general cases of DOALL loops. Our goal is to achieve a computation+communication load balanced partitioning through static data and iteration space distribution. Our approach first performs partitioning of iteration and data spaces of a loop nest by analyzing communication and parallelism; it then performs architecture-dependent analysis to adjust the granularity of partitions, load balance each partition with respect to total computation+communication, and then performs mapping of partitions onto the available number of processors. This multiphase partitioning method works as follows. First, the code partitioning phase analyzes the references in the body of the DOALL loop nest and determines a set of directions for reducing a larger degree of communication by trading a lesser degree of parallelism. The partitioning is carried out in the iteration space of the loop by cyclically following a set of direction vectors such that the data references are maximally localized and reused, eliminating a larger communication volume than parallelism. We then perform data space partitioning based on a new larger partition owns rule to minimize the communication overhead for a compute intensive partition by localizing its references relatively more than a smaller noncompute intensive partition. A partition interaction graph is then constructed which is used by the architecture-dependent analysis phase to merge the partitions to achieve granularity adjustment, computation+communication load balance, and mapping on the actual number of available processors. Relevant theory and algorithms are developed along with a performance evaluation on the Cray T3D.     

基于持久化内存的索引设计重新思考与优化

非易失性内存(non-volatile memory, NVM)是近几年来出现的一种新型存储介质.一方面,同传统的易失性内存一样,它有着低访问延迟、可字节寻址的特性;另一方面,与易失性内存不同的是,掉电后它存储的数据不会丢失,此外它还有着更高的密度以及更低的能耗开销.这些特性使得非易失性内存有望被大规模应用在未来的计算机系统中.非易失性内存的出现为构建高效的持久化索引提供了新的思路.由于非易失性硬件还处于研究阶段,因此大多数面向非易失性内存的索引研究工作基于模拟环境开展.在2019年4月英特尔发布了基于3D-XPoint技术的非易失性内存硬件apache pass (AEP),这使得研究人员可以基于真实的硬件环境去进行相关研究工作.首先评测了真实的非易失性内存器件,结果显示AEP的写延迟接近DRAM,而读延迟是DRAM的3~4倍.基于对硬件的实际评测结果,研究发现过去很多工作对非易失性内存的性能假设存在偏差,这使得过去的一些工作大多只针对写性能进行优化,并没有针对读性能进行优化.因此,重新审视了之前研究工作,针对过去的混合索引工作进行了读优化.此外,还提出了一种基于混合内存的异步缓存方法.实验结果表明,经过异步缓存方法优化后的混合索引读性能是优化前的1.8倍,此外,经过异步缓存优化后的持久化索引最多可以降低50%的读延迟.     

Hyper-Encryption: Eternal Secrecy Using the Bounded Storage and Limited Access Models

ABSTRACT

The efficacy of a cryptosystem rests on the assumptions that are implemented in its security proofs. Computational cryptosystems assume an upper bound on the computational capability of an adversary. A shortcoming of this assumption is that as computing technology advances over time it obviates the processing limitations that are observed or projected when the upper bound was determined. An information theoretic cryptosystem does not make assumptions about the computational capabilities of an adversary and thus it provides the blueprint for cryptosystems that can guarantee the unconditional security of a ciphertext. However, an assumption that both information-theoretic and computational cryptosystems make is that a secret key always remains a secret. Hence, they are both vulnerable to the threat from an adversary who is able to obtain the secret key. Upon obtaining the key the adversary can not only decrypt ciphertexts that are encrypted using the key in the future but also retroactively decrypt those that were encrypted using it in the past. This paper discusses the bounded storage and limited access models and their implementation in hyper-encryption, which is a cryptosystem that assures not only the infinite robustness of a ciphertext but also guarantees its eternal secrecy in the event of key compromise.     

利用FPGA实现DDR存储器控制器

DDRSDRAM以双倍的数据速率已成为存储器的主流,但目前广泛应用的微处理器和数字信号处理器并不支持DDRSDRAM。该文介绍一种通用DDRSRAM控制器的设计,以解决目前所存在的微处理器与DDRSDRAM之间的接口问题。     

Using non-verbal cues to (automatically) assess children’s performance difficulties with arithmetic problems

Intelligent tutoring systems often make use of students’ answers to adapt instruction or feedback on a task. In this paper, we explore the alternative possibility of adapting a system based on the perceived affective and cognitive state of a student. A system can potentially better adapt to the needs of each individual student by using non-verbal behavior. We used a new experimental paradigm inspired by ‘brain training’ software to collect primary school children’s answers to easy and difficult arithmetic problems and made audiovisual recordings of their answers. Adult observers rated these films on perceived difficulty level. Results showed that adults were able to correctly interpret children’s perceived level of difficulty, especially if they saw their face (compared to hearing their voice). They paid attention to features such as ‘looking away’, and ‘frowning’. Then we checked whether we could also automatically predict if the posed problem was either easy or difficult based on the first second of their response. This ‘thin-slice analysis’ could correctly predict the difficulty level in 71% of all cases. When trained on sufficiently many recordings, Adaptive Tutoring Systems should be able to detect children’s state and adapt the difficulty level of their learning materials accordingly.     

用C8051F020的SPI接口扩展大容量数据存储器

本文介绍了一种利用串行外设接口(SPI)为SOC单片机C8051F020扩展大容量数据存储器的设计方案,并给出来软件流程图和示例。该方案充分利用了SPI的功能,在极少地占用单片机引脚的情况下,实现了数据存储器的扩展。     

Using Resolution for Testing Modal Satisfiability and Building Models

This paper presents a translation-based resolution decision procedure for the multimodal logic K _(m)(,,) defined over families of relations closed under intersection, union, and converse. The relations may satisfy certain additional frame properties. Different from previous resolution decision procedures that are based on ordering refinements, our procedure is based on a selection refinement, the derivations of which correspond to derivations of tableaux or sequent proof systems. This procedure has the advantage that it can be used both as a satisfiability checker and as a model builder. We show that tableaux and sequent-style proof systems can be polynomially simulated with our procedure. Furthermore, the finite model property follows for a number of extended modal logics.     

用网络拓扑法论证出游法中两种概率模型的统一

用网络拓扑法分析了出游法中所采用的差分网格概率模型和网络概率模型，从理论上论证了两种模型的统一。由于网络概率模型是由图论场模型法演绎而来，这样就将图论场模型法与出游法紧密联系在一起。为拓宽出游法的应用引出了新的途径，也为在不同的场合下灵活选用这两种数值方法，使它们能充分发挥各自的独特优点提供了方便。     

Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems

The Network-on-Chip (NoC) paradigm brings networks inside chips. We use the routing capabilities inside NoC to serve as a replacement for Virtual Method Table (VMT) for Object-Oriented (OO) designed hardware/software co-design systems where some methods could be implemented as hardware modules. This eliminates VMT area and performance overhead in OO co-designed embedded systems where resources are limited and where some functionality needs to be implemented in hardware to meet performance goals of the system. Our experimental results on real world embedded applications show up to 32.15% lower area and up to 5.1% higher speed compared to traditional implementation using VMT.     

Using Evaluation to Shape ITS Design: Results and Experiences with SQL-Tutor

This paper presents the results of three evaluation studies performed during 1998 and 1999 on SQL-Tutor, an intelligent tutoring system for the SQL database language. We have evaluated the system in the context of genuine courses, and used the results to further refine the system. The main goal of our research has been the exploration and extension of Constraint-Based Modeling (CBM), a student modeling approach proposed by Ohlsson (1994). SQL-Tutor provided us with experiences of using CBM, and we used it to extend the approach in several important ways. The main goal of all three evaluation studies was to determine how well CBM supported student learning. We have obtained positive results. The students who learnt with SQL-Tutor in the first study performed significantly better than those who did not when assessed by a subsequent classroom examination. Furthermore, the analysis of students' learning shows that CBM has a sound psychological foundation.Besides the evaluation of CBM, we also evaluated the improvements in terms of student assessments of the usefulness of the system and evaluated various techniques used in SQL-Tutor. In the second study, we evaluated the effectiveness of feedback provided to the students. This study showed that high-level advice is most beneficial to students' learning. The focus of the third study was different. We extended CBM to support long-term modeling of student knowledge, and used this extension to develop an adaptive problem-selection strategy. The study revealed the benefits of this strategy in comparison with a simple heuristic strategy. We also reflect on our experiences in evaluating SQL-Tutor.