A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

A 5-6.4 Gb/s transceiver, consisting of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO phase-locked loops (PLLs), and a clock recovery unit, was developed. The Tx has a five-tap pre-emphasis filter, and the Rx has an equalizer with an intersymbol interference (ISI) monitor. Monitoring the ISI enables fine adjustment of loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx compensate for transmission losses of up to 20 dB at 6.4 Gb/s, respectively. Both the Tx and Rx channels, including the PLLs, are 3.92 mm/sup 2/ in area. The transmitter dissipates 150 mW/channel at 6.4 Gb/s when compensating for a loss of 20 dB, and the receiver 90 mW/channel when compensating for the same loss.     

基于130 nm CMOS工艺的5 Gbit/s 10:1并串转换芯片

介绍了一种基于GSMC 130 nm CMOS工艺的高速率低功耗10:1并串转换芯片。在核心并串转换部分,该芯片使用了多相结构和树型结构相结合的方式,在输入半速率时钟的条件下,实现了10路500 Mbit/s并行数据到1路5 Gbit/s串行数据的转换。全芯片完整后仿真结果显示,在工作电压(1.2±10%)V、温度-55~100℃、全工艺角条件下,该芯片均可正确完成10:1并串转换逻辑功能,并输出清晰干净的5 Gbit/s眼图。在典型条件下,芯片整体功耗为25.2 mW,输出电压摆幅可达到260 mV。     

基于USB2.0的多路异步串行系统设计

比较了几种扩展串口的方案,针对当前串口在工程中广泛应用的特点,提出了一种利用USB2.0接口芯片(CY7C68013)控制异步串行收发器TL16C554的4路串口通信的方案,设计了适于多路串行数据收发的硬件系统,编写了基于多线程技术的软件系统,实现了USB和串口之间进行通信.测试结果表明:单路波特率可稳定在1 Mbps,4路串口同时传输,每路波特率可稳定在512 Kbps.     

Serially concatenated space-time codes with iterative decoding and performance limits of block-fading channels

This work considers space-time channel coding for systems with multiple-transmit and a single-receive antenna, over space uncorrelated block-fading (quasi-static) channels. Analysis of the outage probability over such channels reveals the existence of a threshold phenomenon. The outage probability can be made arbitrary small by increasing the number of transmit antennas, only if the E/sub b//N/sub 0/ is above a threshold which depends on the coding rate. Furthermore, it is shown that when the number of transmit antennas is increased, the /spl epsi/-capacity of a block-fading Rayleigh channel tends to the Shannon capacity of an additive white Gaussian noise channel. This paper also presents space-time codes constructed as a serial concatenation of component convolutional codes separated by an interleaver. These schemes provide full transmit diversity and are suitable for iterative decoding. The rate of these schemes is less than 1 bit/s/Hz, but can be made arbitrary close to 1 bit/s/Hz by the use of Wyner-Ash codes as outer components. Comparison of these schemes with structures from literature shows that performance gains can be obtained at the expense of a small decrease in rate. Computer simulation results over block-fading Rayleigh channels show that the frame-error rate of several of these schemes is within 2-3 dB from the theoretical outage probability.     

6.0-6.4GHz室内MIMO无线信道测量与传播特性分析

工作在6GHz以上高频段的多输入多输出(Multi-Input-Multi-Output,MIMO)无线通信系统是下一代无线移动通信的有力竞争方案.目前,对制约无线系统性能的高频段空时无线信道特性研究仍较少见.针对这一现状,采用基于网络分析仪的信道测量平台对典型办公环境下6.0-6.4GHz MIMO无线信道特性进行测量和分析.为了明确高频段为系统设计带来的新问题,将测量得到的高频段MIMO信道特性参数与低频段对比.对比结果表明,6.2GHz频段与2.45GHz频段MIMO信道传播特性存在较大差异.在对6.0-6.4GHz室内覆盖MIMO无线通信系统进行设计和评估时,需要基于6.0-6.4GHz频段无线信道传播的新特性对系统的关键技术和方案进行调整.     

A Video Codec Transmitter

The transmitter of a video codec system is designed and realized in ECL hardware. This video codec system is capable of carrying one commercial NTSC color television channel with a program audio channel at a rate of 42.9 Mb/s. The transmitter interfaces with a DPCM processor. The transmitter removes the horizontal blanking interval from the composite television signal, converts the quantized difference signal from the DPCM processor into 4/8-bit dual length code and buffers the codes for constant rate transmission. A line synchronization code is multiplexed with audio and video codes to form a serial data link at 42.9 Mb/s. This can be transmitted on a T3 (44.7 Mb/s) digital carrier. The transmitter is composed of four functional units: controller, coder, buffer and multiplexer. This paper describes the design, layout, testing and evaluation of the high speed digital system that results in 2 to 1 data compression of the digital video.     

Tunable operational transconductance amplifier with extremely high linearity over very large input range

A simply fully-differential transconductor is presented that achieves, based on cancellation of first and higher order nonlinearities, +or-0.7% linearity error over a +or-6.4 V differential input range for +or-5 V power supplies. Common-mode input signals are cancelled at the output. The transconductance can be tuned at least by a factor 3 and f/sub (-3dB)/ is 63 MHz for 10 mu m channel length.<>     

Simple iterative methods to exploit the signal-space diversity

Signal-space diversity is a power- and bandwidth-efficient diversity technique. To exploit the signal-space diversity, joint maximum-likelihood (ML) detection at the receiver is usually needed, where the complexity grows exponentially with the dimension of the lattice. In this letter, we propose a serial concatenated scheme and two simple iterative methods to exploit the signal-space diversity. The simple iterative methods are based on the idea of soft interference cancellation. The first iterative method is based on a vector Gaussian approximation, while the second one is based on a scalar Gaussian approximation. The complexity of the first iterative method grows cubically with the dimension of the lattice, and the simulations show that its performance approaches that of the optimal maximum a posteriori detection method. The complexity of the second iterative method grows linearly with the dimension of the lattice, and the simulations show that when the dimension of the lattice N=32, at bit-error rate =10/sup -5/, the performance gap between the Rayleigh fading channel and the Gaussian channel is only 0.3 dB.     

Improved channel estimator for an HF radio link

The paper describes a novel technique for estimating the sampled impulse-response of a time-varying channel, where the latter involves an HF radio link with two independent Rayleigh fading sky waves. The channel estimator operates on the sampled demodulated baseband signal in the receiver of a synchronous serial data-transmission system, which transmits a 16-level quadrature amplitude modulated signal at 9600 bit/s over the HF radio link. By making a more effective use of the available prior knowledge of the channel the estimator obtains a more accurate estimate of the sampled impulse-response of the channel than that given by more conventional techniques. Results of computer simulation tests are presented to compare the performance of the new estimator with that of an arrangement previously described.     

Pulse amplitude-modulated time-based interface for off-chip interconnect

An increased number of bits pulse amplitude-modulated differential-time signalling interface for off-chip interconnect is introduced in this article by combining the differential time signalling (DTS) technique with the pulse amplitude-modulation (PAM) approach. Applying the PAM to the DTS-transmitted signal increases the total number of the transmitted bits per symbol while maintaining the transmitted signal bandwidth. 4-bit 6 Gb/s DTS serial link has been designed and simulated using 65 nm CMOS mixed signal technology. 5-bit 7.5 Gb/s and 6-bit 9 Gb/s amplitude-modulated DTS serial links have been designed, simulated and compared to the 6 Gb/s DTS serial link. The three serial links use 1.5 Gb/s as input clock signal. In the amplitude-modulated DTS-transmitted signal, the rising and falling edges of the input clock signal are modulated in time as well as the transmitted signal amplitude is modulated. A reference clock pulse is generated from the input clock signal and embedded on the transmitted signal to be used as reference timing at the receiver circuit. The design details of the designed links are presented in the article. The 9 Gb/s link uses a 60 cm 4003C Rogers substrate as a transmission channel. The transmitted signal spectrum is presented and compared for the three designed links. The total power consumption of the 9 Gb/s amplitude-modulated DTS interface is less than 25 mW.     

Multiple serial and parallel concatenated single parity-check codes

Single parity-check (SPC) codes are applied in both parallel and serial concatenated structures to produce high-performance coding schemes. The number of concatenations or stages, M, is increased to improve system performance at moderate-to-low bit-error rates without changing the overall code parameters (namely, code rate and code block length). Analytical bounds are presented to estimate the performance at high signal-to-noise ratios. The SPC concatenated codes are considered with binary phase-shift keying and with 16-quadrature amplitude modulation bit-interleaved coded modulation on the additive white Gaussian noise channel and the independent Rayleigh fading channel. Simulations show that the four-stage serial or parallel concatenated SPC codes can, respectively, outperform or perform as well as 16-state turbo codes. Furthermore, decoding complexity is approximately 9-10 times less complex than that of 16-state turbo codes. The convergence behavior of both serial and parallel concatenated SPC codes is also discussed.     

一种多接口接入系统的网管功能的设计与实现

本多接口接入系统基于光纤环路传输设备，采用同步复接技术，提供多种64Kb／s速率的终端接口。提出了该接入系统网管功能的一种实现方案，利用了现有系统提供的串行通道和E1链路同步时隙提供的20Kb／s通道，设计了多套接入系统与网管PC间的多机通信方式、通信协议、以及接入系统中的控制软件和网管PC中的管理软件，实现了一套灵活有效的网管系统，提高了接入系统的可监管性和易用性。     

SVD iterative detection of turbo-coded multiantenna unitary differential modulation

A new suboptimal demodulator based on a singular value decomposition for estimation of unitary matrices is introduced. Noncoherent communication over the Rayleigh flat fading channel with multiple transmit and receive antennas, where no channel state information is available at the receiver is investigated. Codes achieving bit-error rate (BER) lower than 10/sup -4/ at bit energy over the noise spectral density ratio (E/sub b//N/sub 0/) of 1.6-1.9 dB from code restricted capacity limit were found. At higher data rates, computation of code restricted capacity is impractical. Therefore, the mutual information upper bound of the capacity attaining isotropically random unitary transmit matrices was used. The codes achieve BER lower than 10/sup -4/ at E/sub b//N/sub 0/ of 3.2-6 dB from this bound, with coding rates of 1.125-5.06 bits per channel use, and different modulation decoding complexities. The codes comprise a serial concatenation of turbo code and a unitary matrix differential modulation code. The receiver employs the high-performance coupled iterative decoding of the turbo code and the modulation code. Information theoretic arguments are harnessed to form guidelines for code design and to evaluate performance of the iterative decoder.     

A 3.0 V 40 Mb/s hard disk drive read channel IC

This paper presents a high performance low power BiCMOS mixed signal ASIC that integrates all the electronics required by a hard disk drive (HDD) read channel. The IC includes the automatic gain control (AGC) circuit, a programmable continuous-time filter, two pulse qualifiers, the servo demodulator, the time base generator, the data synchronizer, and the encoder/decoder. Constant density recording with data rates between 14 and 40 Mb/s in 1,7 Run Length Limited (RLL) format and embedded 4-burst servo are supported. All the chip's specifications are guaranteed for supply voltages ranging from 3.0-5.5 V. Programming and testing are achieved via a 3-terminal bi-directional serial interface and internal registers. Nominal power dissipation at 3.0 V supply and 40 Mb/s data rate is 360 mW. Pulse pairing and write data jitter, two key performance parameters, each measured less than 300 ps     

Predicting Microwave Digital Signal Integrity

High-speed digital signal integrity at data rates above 6 Gb/s is an obstacle to reliable serial link operation. Two signal integrity challenges include dispersion due to frequency-dependent losses and reflections created at impedance mismatches. Signal integrity analysis relies on time-domain simulation of pseudo-random data patterns. This paper explores a predictive method for interconnect eye closure caused by reflections at the transmitter and receiver and does not require extensive time domain simulation. Worst-case bounds on intersymbol interference and data-dependent jitter aid prediction for link budgets under channel variations. This method is applied to the design of a passive equalizer.      

Quasi-phase-matched second-harmonic generation indiazo-dye-substituted polymer channel waveguides

First-order quasi-phase-matched (QPM) second-harmonic generation (SHG) is demonstrated in a poled diazo-dye-substituted polymer channel waveguide. The channel waveguide with a nonlinear grating was fabricated by the serial grafting technique using conventional photolithography and reactive ion etching. The dependence of the conversion efficiency on both the waveguide parameter and the grating structure was derived theoretically. A normalized internal conversion efficiency of 1.1% W^-1 cm^-2 at 1.586 μm was obtained in the fabricated waveguide with a phase-matched interaction length of 3.4 mm. The experimentally obtained conversion efficiency is compared with the theoretical value, taking into account the effect of mode-mismatching and propagation loss     

Iterative decoding of space-time differentially coded unitary matrix modulation

Noncoherent communication over the Rayleigh flat fading channel with multiple transmit and receive antennas is investigated. Codes achieving bit error rate (BER) lower than 10/sup -4/ at bit energy over the noise spectral density ratio (E/sub b//N/sub 0/) of 0.8 to 2.8 dB from the capacity limit were found with coding rates of 0.5 to 2.25 bits per channel use. The codes are serial concatenation of a turbo code and a unitary matrix differential modulation code. The receiver is based on a high-performance joint iterative decoding of the turbo code and the modulation code. Information-theoretic arguments are harnessed to form guidelines for code design and to evaluate performance of the iterative decoder.     

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-/spl mu/m CMOS process, the 1.9-mm/sup 2/ transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2/sup 23/-1 PRBS input data with 800-ppm frequency offset.     

Performance Analysis of COFDM for Broadband Transmission on a Fading Multipath Channel

This paper gives a unified analysis of the effects of multipath dispersion and Doppler spreading due to fast fading in OFDM systems, deriving simple closed-form expressions for intersymbol and interchannel interference in the most important cases. It shows also why sine wave carriers are in general the optimum bearers for the sub-channels. The expressions for interference are used to estimate the BER performance of coded OFDM, showing that the use of forward error correction (FEC) coding and a guard period are both essential for optimum performance. As an example it is shown that a 64 sub- channel OFDM system can achieve a data rate of 6.4 Mbit/s on a typical urban mobile radio channel.