LPCVD系统淀积多晶硅薄膜的发雾分析

叙述了采用LPCVD系统淀积多晶硅薄膜的机理,分析了在淀积多晶硅薄膜过程中引起发雾的因素,指出了保持LPCVD系统的洁净能有效消除在淀积多晶硅薄膜过程中出现的发雾现象.     

热壁LPCVD多晶硅膜的质量分析

对就热壁ＬＰＣＶＤ多晶硅的基本原理、典型淀积条件、掺杂、均匀性，引起多晶硅膜层表面“发乌”、“发雾”的原因和提高多晶硅膜质量的工艺措施作了分析和研究。     

多晶硅膜的结构及其性质分析

本文主要叙述低压化学汽相淀积(LPCVD)多晶硅膜的生长机构、多晶硅膜结构、淀积温度与多晶硅膜结构的关系、影响膜层质量的主要因素、引起膜表面“发雾”的原因以及膜的性质。     

微波退火非晶硅薄膜低温晶化研究

多晶硅薄膜晶体管以及其独特的优点在液晶显示领域中起着重要的作用。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（＜600℃高质量多晶硅薄膜已成为研究热点。文章研究了一种低温制备多晶硅薄膜的新工艺;微波退火非晶硅薄膜固相晶化法,利用X射线衍射、拉曼光谱和扫描电镜分析了微波退火工艺对非晶硅薄膜固相晶化的影响,成功实现了低温制备多晶硅薄膜。     

CMOS工艺兼容多晶硅压力敏感膜的设计与加工

在MEMS表面加工工艺中 ,多晶硅薄膜是微结构的重要组成部分。本文考虑加工工艺中残余应力的影响和多晶硅材料的强度范围 ,建立多晶硅膜的大变形模型 ,设计可用于压力传感器应用的多晶硅薄膜几何尺寸。采用有限元方法对多晶硅薄膜进行力学分析和设计验证 ,提出了CMOS工艺兼容的多晶硅压力敏感膜的加工方法 ,并且根据所设计的工艺进行了电容式压力传感器微结构的加工 ,加工结果说明了多晶硅薄膜设计的合理性和CMOS兼容工艺的可行性     

多晶硅/氧化硅界面的二次离子质谱分析

利用二次离子质谱仪对多晶硅/氧化硅界面进行分析,发现多晶硅/氧化硅界面不是突变的,而存在着一个过渡区;根据多晶硅薄膜的成核理论,分析该过渡区形成的物理起源和机理,并利用"氧化层电导"模型,定量分析过渡区对器件栅氧化层电导的影响.     

CMOS工艺兼容多晶硅压力敏感膜的设计与加工

在MEMS表面加工工艺中,多晶硅薄膜是微结构的重要组成部分.本文考虑加工工艺中残余应力的影响和多晶硅材料的强度范围,建立多晶硅膜的大变形模型,设计可用于压力传感器应用的多晶硅薄膜几何尺寸.采用有限元方法对多晶硅薄膜进行力学分析和设计验证,提出了CMOS工艺兼容的多晶硅压力敏感膜的加工方法,并且根据所设计的工艺进行了电容式压力传感器微结构的加工,加工结果说明了多晶硅薄膜设计的合理性和CMOS兼容工艺的可行性.     

多晶硅薄膜的高温压阻效应

利用LPCVD制备重掺杂多晶硅薄膜,在0～560℃温度范围内对薄膜的压阻效应进行研究,同时对多晶硅薄膜应变系数随温度的变化,以及薄膜的淀积温度与薄膜厚度对应变系数的影响进行了相关的实验研究.结果表明,利用多晶硅材料制作的压敏电阻,其最高工作温度可以达到560℃以上.     

多晶硅薄膜的高温压阻效应

利用LPCVD制备重掺杂多晶硅薄膜,在0～560℃温度范围内对薄膜的压阻效应进行研究,同时对多晶硅薄膜应变系数随温度的变化,以及薄膜的淀积温度与薄膜厚度对应变系数的影响进行了相关的实验研究.结果表明,利用多晶硅材料制作的压敏电阻,其最高工作温度可以达到560℃以上.     

铝诱导晶化法制备多晶硅薄膜

多晶硅薄膜在微电子和能源科学领域有着广泛的应用。本文介绍了利用铝诱导晶化非晶硅制备多晶硅薄膜的方法,叙述了铝诱导晶化法制备多晶硅薄膜的一般过程,着重讨论了铝诱导晶化非晶硅的机理和在制备过程中各种参数对多晶硅薄膜质量的影响。     

采用暗态点光源模型的夜间去雾算法

针对夜间雾、霾场景下的去雾图像存在颜色失真、纹理损失、亮度低等缺陷,本文提出了一种采用暗态点光源模型的夜间去雾算法,通过构建夜间雾、霾场景的暗态点光源模型,利用联合双边滤波、限制对比度自适应直方图均衡化等算法对降质图像进行处理,结合大气散射模型得到去雾图像.实验结果表明,该算法的处理速度快、夜间去雾效果较好,较对比算法...     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

Reduced PFC emissions and gas consumption using a c-C/sub 4/F/sub 8/-based PECVD chamber clean chemistry

Perfluorocompounds (PFCs) used in semiconductor manufacturing are potential contributors to greenhouse gas-driven climate change. PFCs emitted from plasma enhanced chemical vapor deposition (PECVD) chamber cleans can be a significant portion of the total PFC emissions for a typical semiconductor fabrication facility. Previous work adopting octafluorocyclobutane (c-C/sub 4/F/sub 8/) clean chemistries to reduce gas consumption and PFC emissions have been reported on applied materials and novellus PECVD tools. In this study, c-C/sub 4/F/sub 8/ was evaluated as an alternative chamber clean gas on Mattson ASPEN II PECVD tools. A statistical design of experiment (DOE) methodology and tool emission analysis by Fourier transform infrared spectrometry were used to develop a low gas consumption and low PFC emission process. This c-C/sub 4/F/sub 8/ process reduced the clean gas consumption by 65% and PFC emission by 78%, compared to our current C/sub 2/F/sub 6/ clean with no impact on deposited film properties or process repeatability.     

Impact of interface nature on deep sub-micron Al-plug resistance

Sputter clean had been accepted as an effective surface clean process prior to metal deposition. In this work, the impact of interface nature on via resistance of Al-interconnect as via size is scaled down to 0.16 μm was studied. Al–F compound was identified as the main interfacial contaminants after standard post-etch clean process if the TiN layer of the underlying metal line were etched through during via etch. For via size larger than 0.25 μm (aspect ratio lower than 3.2), Al–F compound can be removed by sputter clean effectively. However, below 0.25 μm, sputter clean efficiency decreases such that via resistance is degraded by the existence of Al–F interfacial layer. On the other hand, sputter clean results in oxide re-deposition, which in turn degrades via resistance. It is suggested that to obtain low resistance sub-0.2 μm via, via etch must stop on TiN layer such that no Al–F layer can be formed. Otherwise, new interfacial layer clean technology with high efficiency and without side effect has to be developed.     

基于图像深度重定义的雾天车道线特征提取

为了解决雾天车道线特征不清晰、车道线特征分割阈值选取困难的问题,提出了一种结合图像深度重定义去雾模型的雾天车道线特征提取方法.首先,将采集装置与道路之间的实际场景映射到几何模型上.其次,在抽象好的几何模型上提出图像深度图的定义,并根据图像深度图以及雾天图像模型计算去雾之后的图像.最后,利用图像HSV颜色模型,构建图像分割模型,对车道线特征和非车道线特征进行初步分割,并结合OSTU阈值调优方法对车道线特征进行二次分割.实验结果显示,去雾之后车道线特征清晰,阈值分割比传统的OSTU分割效果更好,最终非车道线特征的占比要比基于灰度算法的平均减少14％.     

Stretchable Anti-Fogging Tapes for Diverse Transparent Materials

Surface wetting prevents surface fogging on transparent materials by facilitating filmwise condensation with specific chemistry, but suffers from material and geometry selectivity. Extreme environments associated with high humidity and mechanical loading further limit their anti-fogging persistence. Here, a stretchable anti-fogging tape (SAT) that can be applied to diverse transparent materials with varied curvatures for persistent fogging prevention is reported. The SAT consists of three synergistically combined transparent layers: i) a stretchable and tough layer with large elastic recovery, ii) an endurant anti-fogging layer insensitive to ambient humidity, and iii) a robustly and reversibly adhesive layer. The SAT maintains high total transmittance (>90%) and low diffuse transmittance (<5%) in high-humidity environments, under various modes of mechanical deformations, and over a prolonged lifetime (193 days tested so far). Two applications are demonstrated, including the SAT-adhered eyeglasses and goggles for clear fog-free vision, and the SAT-adhered condensation cover for efficient solar-powered freshwater production.     

Low temperature,defect-free silicon epitaxy using a low kinetic energy particle process

Concurrent bombardment of a growing film surface by Ar ions having low kinetic energies comparable to typical inter-atomic binding energies has been utilized to activate the film surface. It has been shown that such activation is quite effective and can be substituted for substrate heating during crystal growth. As a result, high quality, device grade epitaxial silicon films have been successfully grown at very low temperatures of 250°–300° C. In this epitaxial growth process, dopant impurities in the target are fully incorporated into the grown film and 100% electrically activated at such low temperatures. The direction for further reducing the epitaxial silicon growth temperature has been examined experimentally, and it is shown that the establishment of anultra clean processing environment andultra clean wafer surface as well asperfect process parameter control are quite essential for very low temperature silicon epitaxy.     

Damage-Free Cryogenic Aerosol Clean Processes

Cryogenic aerosol clean processes have been successful for cleaning of blanket films and robust device structures. As the line width becomes smaller and aspect ratios (ARs) become higher, they have either been eliminated or used with caution due to line damage. Theoretical line damage modeling indicates that collision induced stress in line structures is a function of the AR of line cross section. Theoretical analysis also shows that smaller and lighter cryogenic aerosol crystal is desired to avoid line damage. Nitrogen cryogenic aerosol processes have been evaluated for damage-free cleaning on 90 and 65 nm technologies at the IBM 300 mm manufacturing line. Process results on the 90 nm technology at the post spacer nitride deposition clean have shown no damage and particle removal efficiency (PRE) greater than 92%. Implementation of the same nitrogen only aerosol process at the post cobalt silicide probe test clean on 90 nm high AR gate structures has shown significant improvement over the previous process of record argon/nitrogen-based aerosol. Evaluation at the post nickel silicide probe test clean on 65 nm device technology with low AR gate structures has shown the process is damage-free with particle removal efficiency greater than 95%. This nitrogen only aerosol process has been implemented in the 65 nm technology flow and has been proven to be damage-free in volume manufacturing     

关于中国洁净煤技术发展的若干思考

中国发展洁净煤技术应覆盖煤炭开发利用的全过程,针对多终端用户,优选实用的先进技术。中国的洁净煤技术是以提高煤炭利用效率、减少污染为目标,以煤炭洗选为源头,以煤炭气化为先导,以煤炭高效洁净燃烧和洁净煤发电为核心的技术体系。框架包括4个领域共12个方面:煤炭加工(选煤,型煤,水煤浆);煤炭高效洁净燃烧(流化床燃烧,高效低污染粉煤燃烧,燃煤联合循环发电);煤炭转化(气化,液化,燃料电池);污染控制(烟气净化,粉煤灰综合利用,矿区污染治理)。