An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted N-channel MOSFET's

In relatively heavily and deeply boron-implanted n-channel MOSFET's, we found the anomalous phenomenon that the threshold voltage increases with decreasing channel length over a wide range of channel lengths. This is quite contrary to the well-known short-channel effect associated with the dependence of the threshold voltage on the channel length. It is difficult to explain this phenomenon directly by any simplified models that have been presented to date. In this brief, we present mainly the detailed experimental results of such an anomalous short-channel effect.     

Effects of injection resistance on the performance of very-short-channel MOSFET's

Injection resistance, the spreading resistance due to current crowding at the source end of an FET channel, can lead to considerable performance reduction in short-channel MOSFET's. A simple technique for determining the magnitude of this resistance by means of measurements in the linear operation region is described. A simple analytical model which incorporates the effects of both velocity saturation and injection resistance is also developed. The method and model are experimentally verified by determination of the effects of injection resistance on MOSFET's with channel lengths from 0.2 to 24.6 µm.     

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.     

Effects of interfacial Oxide layer on short-channel polycrystalline source and drain MOSFET's

Using a novel self-alignment approach, the characteristics of polycrystalline source and drain MOSFET's with and without a deliberately grown oxide under the polycrystalline regions are compared. The interfacial oxide is shown to suppress short-channel effects in the shortest channel devices studied, but this improvement is at the expense of increased source-to-drain contact resistance in the present devices. The devices without the interfacial oxide are also expected to have superior hot-carrier performance.     

Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET's in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V_th) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the ΔV_th of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices     

Indium channel implant for improved short-channel behavior ofsubmicrometer NMOSFETs

Indium has been used as an alternative channel implant in submicrometer-channel Si MOSFETs in order to obtain highly nonuniform channel doping. Superior device characteristics have been obtained down to 0.17-μm channel length. The device characteristics have been compared to those of uniform boron-implanted short-channel MOSFETs used in a 0.25-μm CMOS technology. Results indicate that NMOSFETs with nonuniform channel doping obtained with indium have superior short-channel effect (SCE) when compared to NMOSFETs with uniformly (boron) doped channel     

Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10^-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.     

SOS MOSFET two-dimensional analysis

Two-dimensional analysis of short-channel SOS MOSFET's is presented, The analysis is based on the circular-field-line approximation to determine the boundary conditions in the sapphire substrate. Si-sapphire interface-state effects are taken into account. Using this analysis method, short-channel SOS MOSFET characteristics were investigated. The electric-field lines, originating from the drain, are terminated not only in the Si substrate charge but also in the interface states. The interface states can suppress the short-channel effects in either n- or p-channel SOS MOSFET's. Predicted characteristics agree with the experimental results.     

Measurement of MOSFET substrate dopant profile via inversionlayer-to-substrate capacitance

In this paper, a new method for extracting substrate dopant concentration profile of short-channel MOSFET's is presented. It is based on the measurement of the small-signal capacitance between the inversion layer and the substrate. The method achieves effective deep depletion through dc reverse bias on the inversion-to substrate junction and thus avoids the problems with transients associated with pulsed C-V of MOS capacitors. By using transistors of different drawn lengths the effect of lateral extension of drain and source junction depletion regions is also accounted for     

Design of ion-implanted MOSFET's with very small physical dimensions

This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.     

An analytical breakdown model for short-channel MOSFET's

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.     

Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's

Intrinsic capacitance of lightly doped drain (LDD) MOSFET's is measured by means of a four-terminal method without using any on-chip measurement circuits. The gate-to-drain capacitance Cgdof LDD MOSFET's is smaller than that of conventional MOSFET's in the saturation region. The technique is applied to determine the effective channel length.     

On the accuracy of channel length characterization of LDD MOSFET's

A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n^-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFET's. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFET's.     

An accurate intrinsic capacitance modeling for deep submicrometerMOSFET's

This paper presents a new approach to the modeling of MOSFET capacitive characteristics for accurate simulation of deep submicrometer integrated circuits. The C-V characteristics of our new quasistatic intrinsic capacitance model accurately describes the short channel effects of deep submicrometer MOSFET's by accounting for velocity saturation and series resistance effects. The use of charge equations consistent with the short channel I-V characteristics leads to C-V characteristics which preserve all major short channel effects. The C-V calculation, based on nonpinned surface potential approach and drift-diffusion model, shows highly accurate short-channel effects and inherently smooth transitions for all conditions of device operation. The accuracy of the C-V characteristics has been demonstrated by comparison with the Ward-Dutton model and PISCES simulation results     

Flat-band voltage dependence on channel length in short-channel threshold model

This paper describes a modified short-channel threshold model that incorporates the flat-band voltage dependence on the channel length. Results obtained from the threshold voltage measurement on n-channel MOSFET's before and after total dose radiation are in good agreement with the proposed model.     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained     

Estimation of doping profiles in short channel MOSFET's using DC Measurements

Estimation of impurity profiles in short channel enhancement-mode MOSFET's using the dc measurement technique is studied. The use of long channel theory predicts erroneous impurity profiles for devices with channel lengths of less than 6 µm. A new empirical model for substrate charge sharing is presented which provides good agreement between profiles estimated by measurements on identically doped long and short channel MOSFET's. It is found that the dc measurement technique can be extended to enhancement-mode MOSFET's with channel lengths as small as 2.5 µm.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.