Logarithmic analog-to-digital converter

Translated from Izmeritel'naya Tekhnika, No. 5, pp. 4–6, May, 1989.     

A broadband analog-to-digital converter of sinusoidal voltages

A block diagram and an algorithm of the operation of a broadband analog-to-digital converter of sinusoidal voltages are presented. The choice of the parameters is considered. Estimates of the speed of response are obtained. __________ Translated from Izmeritel’naya Tekhnika, No. 3, pp. 37–40, March, 2008.     

An integration-type high-speed analog-to-digital converter

An analog-to-digital (A/D) converter consisting of a switched-capacitor integrator, comparator, and control circuit is presented. The conversion process consists of voltage-to-frequency (V/F) conversion to determine the upper M bits of an N-bit representation of an analog input voltage and the subsequent voltage-to-time (V/T) conversion to determine the remaining lower N -M bits. The total clock cycle required for N-bit resolution is 2^M+2^N-M at most. The circuits for the V/F and V/T conversion share most of the components and thus the converter can be implemented with the minimum component count. Error analysis shows that a conversion accuracy higher than 12 bits can be expected from its CMOS monolithic realization. Prototype converters built using discrete components have confirmed the principles of operation     

A 1-Ms/s 16-bit analog-to-digital converter

The author describes a 1-Ms/s. 16-bit analog-to-digital converter (ADC) that uses a subranging conversion technique. High accuracy at 1-MHz conversion rate is obtained with novel circuits developed for a track-and-hold (T/H), a residue amplifier, and a digital-to-analog converter (DAC). Design aspects of these key functional circuits are presented. A prototype ADC was fabricated on a PC board and tested. The results of curve fit tests show that, up to 100 kHz, effective bits are better than 16. However, signal bandwidth is commonly restricted in spectrum analysis; therefore, a dynamic range of over 96 dB can be obtained     

Dynamic model of bitwise-balancing analog-to-digital converter

A dynamic model of a bitwise-balancing analog-to-digital converter that allows for the main factors influencing accuracy is described. The probability characteristics of the dynamic error are obtained and recommendations for its reduction are provided. Translated from Izmeritel'naya Tekhnika, No. 7, pp. 53–56, July, 2000.     

An algorithm analog-to-digital converter using unity-gain buffers

An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8-b and a conversion rate up to 10 Mb/s are attainable with presently available 3-μm CMOS technologies. Video frequency operation is also possible with finer linewidths. The component requirement is minimum, and thus it is best suited for an analog interface in application-specific integrated circuits (ASIC). A prototype cyclid A/D converter built using discrete components confirms the principles of operation     

Dynamic demonstration of diffractive optic analog-to-digital converter scheme

Dynamic behavior of an analog-to-digital converter (ADC) based on diffractive optical element(s) (DOE)(s) was studied and found to be in agreement with predictions. The analog signal was translated to an angular deflection of a laser beam by means of an acousto-optic (AO) cell. The number of bits in this experimental demonstration was three, using an eight-element DOE array. The maximum sample rate was found to be 2.5 MS/s, the limiting factor being the transit time for the acoustic wave across the width of the laser beam in the AO cell. The study is intended as a first dynamic demonstration of a proposed ADC scheme previously demonstrated in a quasi-static version. The full potential of the ADC scheme will require the use of a fast tunable diode laser to replace the AO deflection scheme used here.     

Instrumental resistance-frequency converter chip

A special-purpose analog integrated circuit chip is described that converts the ratio between the temperature transducer resistance to a certain reference resistance into repetition period of pulses of fixed duration. The chip includes circuits for resistance current and current-oscillation period converters, and a current pulse generator in the power supply section. Stability of converter parameters is ensured by using supplies with temperature-stabilized current drift.Translated from Izmeritel'naya Tekhnika, No. 11, pp. 52–54, November, 1994.     

低损耗电光模数转换器的分析与设计

提出采用有限差分束传输法设计出微棱镜相位补偿的2位电光A/D转换器的波导结构参数。利用保角变换方法对转换器的电极参数进行分析与设计。最后,得到优化参数:带宽?f=3.71GHz,特征阻抗49.76?,半波电压Vπ=9.25V,归一化功率输出为56.86%,波导输出间隔为250μm,器件长度为30mm。     

Methodological component of the dynamic error of a position-balance analog-to-digital converter

Translated from Izmeritel'naya Tekhnika, No. 3, pp. 12–13, March, 1988.     

Stochastic analog-to-digital converter based on the asynchronoussampling of a reference triangle

An analog-to-digital (A/D) converter is presented based on the repeated comparison at random intervals of the input voltage with the instantaneous value of a triangular waveform. This asynchronous sampling of a triangular waveform results in a converter, which features simplicity, both in conversion principle and circuit design, as the linearity merely depends on short-term stability of nonprecision components. The resolution increases with the number of samples and a tradeoff is possible between resolution and conversion time. In intelligent sensors the transducer, the signal conditioning circuits, and the A/D converter are integrated in a single chip. The required IC-process compatibility of all these subsystems narrows the range of the possibilities for implementing special processing steps to realize precision components, which favors the application of the stochastic A/D converter     

Method of optimizing the sampling frequency in analog-to-digital signal analysis

A method is proposed for determining the optimum sampling frequency in the analog-to-digital analysis of signals in measurement technology. Having this frequency and knowing the characteristics of the input signal, it becomes possible to account for the dynamic characteristics of the analog channel of an analog-to-digital converter and the effect of noise in its sampled output signal. An example is presented to illustrate the calculation of the optimum sampling frequency. Translated from Izmeritel'naya Tekhnika, No. 10, pp. 33–41, October, 1997.     

Development of the integrating analog-to-digital converter fordistributive data acquisition systems with improved noise immunity

Requirements for the noise immunity of the universal ADC for sensor signal conversion are formulated. The structure of the antijamming dual slope ADC for use in distributive adaptive and intelligent measurement and control systems is described. The normal mode rejection calculated by simulation of ADC operating modes and by experimental research is compared. It has been shown that the sets of operating modes of the developed ADC compared with adaptive properties provide high flexibility of this ADC for determining metrology characteristics of the developed ADC setting