Blanket LVD tungsten silicide technology for smart powerapplications

A high-frequency power MOSFET structure fabricated using blanket deposited LPCVD (low-pressure chemical vapor deposition) WSi₂ gate and selectively deposited LPCVD tungsten source contact metallurgy is reported. A high-density power MOSFET technology suitable for smart power applications which simultaneously lowers the gate sheet resistance and source contact resistance is discussed. This technology was used to fabricate 30-V and 50-V power FETs with excellent high-frequency performances. The measured specific on-resistance R_sp, specific input capacitance C_sp , and switching times are among the lowest reported in the literature for any power FET structure in this reverse blocking voltage range     

A high-voltage optoelectronic GaAs static induction transistor

Experimental realization of an optically activated, high-voltage GaAs static induction transistor (SIT) is reported. In the forward blocking state, the breakdown voltage of the device was ~200 V, while in the conduction state, on-state current densities exceeding 150 A/cm² were obtained. In the floating-gate configurations (gate open), the specific on-resistance of the device was ~50 mΩ-cm². Optical modulation of the device was achieved using a compact semiconductor laser array as the triggering source. In this mode, a gate-coupled RC network was implemented, resulting in an average switching energy gain (load energy/optical energy) of ~30. This mode of operation is applicable to series-coupled devices for pulsed switching at higher power levels     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Self-aligned gate and source drain contacts in inverted-staggereda-Si:H thin-film transistors fabricated using selective area siliconPECVD

This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned ion resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm² /Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is <10^-11 A with -10 V gate voltage and 10 V between the source and drain, and ON/OFF ratios exceed 10     

一种200V/100A VDMOS器件开发

分析了功率MOSFET最大额定电流与导通电阻的关系,讨论了平面型中压大电流VDMOS器件设计中导通电阻、面积和开关损耗的折衷考虑,提出了圆弧形沟道布局以增大沟道宽度,以及栅氧下部分非沟道区域采用局域氧化技术以减小栅电容的方法,并据此设计了一种元胞结构。详细论述了器件制造过程中的关键工艺环节,包括栅氧化、光刻套准、多晶硅刻蚀、P阱推进等。流水所得VDMOS实测结果表明,该器件反向击穿特性良好,栅氧耐压达到本征击穿,阈值电压2.8V,导通电阻仅25mΩ,器件综合性能良好。     

High-frequency power MOSFETs fabricated using selectively deposited LPCVD tungsten

A novel high-density, high-frequency power MOSFET structure fabricated using selectively deposited LPCVD tungsten on gate polysilicon and source contact regions is reported. The gate-to-source isolation was provided by anisotropically etched phosphosilicate glass (PSG) spacers. Using this technology, the author has successfully fabricated 30 V power DMOS FETs with excellent high-frequency switching performance in terms of low specific on-state resistance R/sub sp/=0.5 m Omega cm/sup 2/, low specific input capacitance C/sub sp/=43 nF/cm/sup 2/, and high switching speed: t/sub on/ and t/sub off/<2 ns. These results represent the first successful demonstration of complex device structures fabricated using LPCVD tungsten derived process technology.<>     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

A novel simplified process for fabricating a very high densityp-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch²) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 mΩ-cm² with a breakdown voltage of -36 V     

High-voltage bipolar mode JFET with normally off characteristics

The first realization of a power vertical JFET operated in the bipolar mode (BJFET) with normally off behavior is reported. The structure combines minority carrier injection from the gate region in the on-state, and lateral pinch-off of the channel, due to the built-in voltage, in the off-state. The realized devices show high blocking voltages, up to 900 V, with zero gate bias, and have extremely low on-resistance. Fast switching speeds with forced gate turn-off times as low as 100 ns for devices of 600-V blocking voltages have been obtained.     

A power junction gate field-effect transistor structure with high blocking gain

A new gate structure is described for vertical-channel power junction gate field-effect transistors (FET's). This gate structure has vertically walled gate regions extending perpendicular to the wafer surface. The structure is fabricated by using orientation-dependent silicon etching and selective vapor-phase epitaxial refill techniques. In comparison to previous gate structures made by planar diffusion, the vertically walled gate structure exhibits one order of magnitude improvement in blocking gain. This improvement in blocking gain has allowed the fabrication of devices having breakdown voltages above 400 V and a current-handling capability of more than 0.5 A with an on-resistance of 12 Ω. The devices are designed to exhibit pentode-like characteristics at low gate voltages and triode-like characteristics at large reverse gate bias voltages in order to obtain the observed high-power handling capability.     

On-State Characteristics of SiC power UMOSFETs on 115-/spl mu/m drift Layers

We describe the on-state performance of trench oxide-protected SiC UMOSFETs on 115-/spl mu/m-thick n-type 4H-SiC epilayers designed for blocking voltages up to 14 kV. An on-state current density of 137 A/cm/sup 2/ and specific on-resistance of 228 m/spl Omega//spl middot/cm/sup 2/ are achieved at a gate bias of 40 V (oxide field of 2.67 MV/cm). The effect of current spreading on the specific on-resistance for finite-dimension devices is investigated, and appropriate corrections are made.     

Double gate lateral IGBT on partial membrane

A new SOI LIGBT(lateral insulated-gate bipolar transistor)with cathode-and anode-gates on partial mem-brahe is proposed.A low on-state resistance is achieved when a negative voltage is applied to the anode gate.In the blocking state,the cathode gate is shortened to the cathode and the anode gate is shortened to the anode,leading to a fast switching speed.Moreover,the removal of the partial silicon substrate under the drift region avoids collecting charges beneath the buried oxide,which releases potential lines below the membrane,yielding an enhanced breakdown voltage(BV).Furthermore,a high switching speed is obtained due to the absence of the drain-substrate capacitance.Lastly,a combination of uniformity and variation in lateral doping profiles helps to achieve a high BV and low special on-resistance.Compared with a conventional LIGBT,the proposed structure exhibits high current capability,low special on-resistance,and double the BV.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

The accumulation-mode field-effect transistor: a new ultralowon-resistance MOSFET

An ultralow specific on-resistance, vertical channel, power MOSFET structure, based on current conduction via an accumulation layer formed on the surface of a trench (UMOS) gate structure, is described. Two-dimensional numerical simulations and experimental results have been obtained, demonstrating that a specific on-resistance approaching 100 μΩ-cm² can be obtained for a silicon device capable of blocking 25 V     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

Silicon Carbide Power MOSFET Model and Parameter Extraction Sequence

A compact circuit simulator model is used to describe the performance of a 2-kV, 5-A 4-H silicon carbide (SiC) power DiMOSFET and to perform a detailed comparison with the performance of a widely used 400-V, 5-A Si power MOSFET. The model's channel current expressions are unique in that they include the channel regions at the corners of the square or hexagonal cells that turn on at lower gate voltages and the enhanced linear region transconductance due to diffusion in the nonuniformly doped channel. It is shown that the model accurately describes the static and dynamic performance of both the Si and SiC devices and that the diffusion-enhanced channel conductance is essential to describe the SiC DiMOSFET on-state characteristics. The detailed device comparisons reveal that both the on-state performance and switching performance at 25degC are similar between the 400-V Si and 2-kV SiC MOSFETs, with the exception that the SiC device requires twice the gate drive voltage. The main difference between the devices is that the SiC has a five times higher voltage rating without an increase in the specific on-resistance. At higher temperatures (above 100degC), the Si device has a severe reduction in conduction capability, whereas the SiC on-resistance is only minimally affected     

SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。