Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).     

Void detection in solder bumps with deep learning

Wafer level chip scale packages feature large numbers of solder bumps. These bumps are prone to having voids arising for instance from outgassing during the solder reflow. These voids are considered a reliability risk for the thermo-mechanical strength of the solder connection. Screening of bumps on void percentage is therefore required for quality control. Voids are well captured with X-ray radiography. Void detection in X-ray images is the topic of this paper. The large number of solder bumps necessitates the detection to be automated. In this article we first employ conventional threshold based methods to identify voids. Then, we apply a deep learning model to void percentage detection. We will demonstrate that with a proper training data set deep learning can successfully bin solder bumps on their void percentage.     

Characterization of small-sized eutectic Sn-Bi solder bumps fabricated using electroplating

We studied the effects of the cooling rate during the reflow process on the microstructure of eutectic Sn-Bi solder bumps of various sizes fabricated by electroplating. To fabricate eutectic Sn-Bi solder bumps of less than 50 μm in diameter, Sn-Bi alloys were electroplated on Cu pads and reflowed at various cooling rates using the rapid thermal annealing system. The interior microstructure of electroplated bumps showed a fine mixture of Sn-rich phases and Bi-rich phases regardless of the cooling rate. Such an interior microstructure of electroplated bumps was quite different from the reported microstructure of vacuum-evaporated bumps. Ball shear tests were performed to study the effects of the cooling rate on the shear strength of the solder bumps and showed that the shear strength of the bumps increased with increasing cooling rate probably due to the reduced grain size. Soft fractures inside the solder bump were observed during the ball shear test regardless of the cooling rate.     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

Anisotropic behavior of the capillary action in flip chip underfill

An underfill encapsulant can be used to improve the long-term reliability of flip chip interconnecting system by filling the gap between the chip and substrate around the solder bumps. The underfill encapsulant was filled by a capillary flow. This study was devoted to investigate the anisotropic effects of the capillary action induced by the solder bumps. A modified Hele-Shaw flow model, considering the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. A capillary force model, depending on the direction of filling flow, for full array solder bumps was proposed. The capillary force was formulated based on quadrilateral arrangement of solder bumps. It was found that the capillary action is not the same for different directions. In the 45° direction, enhancement of the capillary flow was noticed for a bump pitch within a critical value. The edge preferential flow during the underfill experiment could be attributed to the anisotropic behavior of the capillary action.     

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated.      

Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.     

3D-MCM的X射线检测分析

X射线检测技术是一种能对不可视部位进行检测的技术。本文利用X射线对3D—MCM中的BGA焊点、基板和隔板之间的焊料凸点、叠层基板间的垂直互连和陶瓷-金属封装等进行检测;对存在于焊点和凸点中的气孔、垂直互连中的开路和封装中的孔洞等进行了分析。     

Microstructure characterization of Sn-Ag solder joints between stud bumps and metal pads

The microstructure of the flip-chip solder joints fabricated using stud bumps and Pb-free solder was characterized. The Au or Cu stud bumps formed on Al pads on Si die were aligned to corresponding metal pads in the substrate, which was printed with Sn-3.5Ag paste. Joints were fabricated by reflowing the solder paste. In the solder joints fabricated using Au stud bumps, Au-Sn intermetallics spread over the whole joints, and the solder remained randomly island-shaped. The δ-AuSn, ε-AuSn₂, and η-AuSn₄ intermetallic compounds formed sequentially from the Au stud bump. The microstructure of the solder joints did not change significantly even after multiple reflows. The AuSn₄ was the main phase after reflow because of the fast dissolution of Au. In the solder joints fabricated using Cu stud bumps, the scallop-type Cu₆Sn₅ intermetallic was formed only at the Cu interface, and the solder was the main phase. The difference in the microstructure of the solder joints with Au and Cu stud bumps resulted from the dissolution-rate difference of Au and Cu into the solder.     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。     

Correlation between interfacial reactions and mechanical strengths of Sn(Cu)/Ni(P) solder bumps

The correlation between interfacial reactions and mechanical strengths of Sn(Cu)/Ni(P) solder bumps has been studied. Upon solid-state aging, a diffusion-controlled process was observed for the interfacial Ni-Sn compound formation of the Sn/Ni(P) reaction couple and the activation energy is calculated to be 42 KJ/mol. For the Sn0.7Cu/Ni(P), in the initial aging, a needle-shaped Ni-Sn compound layer formed on Ni(P). Then, it was gradually covered by a layer of the Cu-Sn compound in the later aging process. Hence, a mixture layer of Ni-Sn and Cu-Sn compounds formed at the interface. For the Sn3.0Cu/Ni(P), a thick Cu-Sn compound layer quickly formed on Ni(P), which retarded the Ni-Sn compound formation and resulted in a distinct Cu-Sn compound/Ni(P) interface. The shear test results show that the mixture interface of Sn0.7Cu bumps have fair shear strengths against the aging process. In contrast, the distinct Cu-Sn/Ni(P) interface of Sn3.0Cu solder bumps is relatively weak and exhibits poor resistance against the aging process. Upon the reflowing process, the gap formation at the Ni(P)/Cu interface caused a fast degradation in the interfacial strength for Sn solder bumps. For Sn0.7Cu and Sn3.0Cu solder bumps, Ni₃P formation was greatly retarded by the self-formed Cu-Sn compound layer. Therefore, Sn(Cu) solder bumps show better shear strengths over the Sn solder bump.     

Preparation of Sn-Ag-In ternary solder bumps by electroplating in sequence and reliability

This paper describes a technique that can obtain ternary Sn-Ag-In solder bumps with fine pitch and homogenous composition distribution.The main feature of this process is that tin-silver and indium are electroplated on copper under bump metallization（UBM） in sequence.After an accurate reflow process,Sn_1.8Ag_9.4In solder bumps are obtained.It is found that the intermetallic compounds（IMCs） between Sn-Ag-In solder and Cu grow with the reflow time,which results in an increase in Ag concentration in the solder area.So during solidification, more Ag₂In nucleates and strengthens the solder.     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Effects of Co addition in eutectic Sn-3.5Ag solder on shear strength and microstructural development

In this study, the approach of composite solder using eutectic Sn-3.5Ag solder and Co was tried. Co particles and Sn-3.5Ag solder paste were mechanically mixed at Co weight fractions from 0.1% to 2.0%. For the Co-mixed Sn-3.5Ag solder pastes, their melting temperatures and spreading areas were measured. The solder pastes were stencil printed on test substrates and reflowed to form solder bumps. Ball shear test was performed to examine shear strength of Co-reinforced Sn-3.5Ag solder bumps. As a result, Co addition up to 2 wt.% did not alter the melting temperature under heating but reduced undercooling. The maximum shear strength of Co-reinforced Sn-3.5Ag solder bumps increased by 28% compared to normal ones. The increase in shear strength can be attributed to the (Cu,Co)₃Sn₂ intermetallic compounds.     

Effect of Grain Boundary Misorientation on Electromigration in Lead-Free Solder Joints

Reduction in microelectronic interconnect size gives rise to solder bumps consisting of few grains, approaching a single- or bicrystal grain morphology in C4 bumps. Single grain anisotropy, individual grain orientation, presence of easy diffusion paths along grain boundaries, and the increased current density in these small solder bumps aggravate electromigration. This reduces the reliability of the entire microelectronic system. This paper focuses on electromigration behavior in Pb-free solder, specifically the Sn-0.7 wt.%Cu alloy. We discuss the effects of texture, grain orientation, and grain boundary misorientation angle on electromigration (EM) and intermetallic compound formation in EM-tested C4 bumps. The detailed electron backscatter diffraction (EBSD) analysis used in this study reveals the greater influence of grain boundary misorientation on solder bump electromigration compared with the effect associated with individual grain orientation.     

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

一种低成本倒装芯片用印刷凸焊点技术的研究

利用化学镀底部金属化层结合丝网印刷制作凸焊点的技术,通过剪切实验得到了凸焊点的剪切强度,用电子显微镜对失效表面进行了分析研究,应用SEM及EDAX分析了凸焊点的组织结构与成分变化,对热老炼后凸焊点的强度变化进行了研究。结果表明凸焊点内部组织结构的变化是剪切失效的主要原因。经X光及扫描声学显微镜检测,表明组装及填充工艺很成功。对已完成及未进行填充的两种FCOB样品进行热疲劳实验对比,发现未进行填充加固的样品在115周循环后出现失效,而经填充加固后的样品通过了1 000周循环,表明下填料明显延长了倒装焊封装的热疲劳寿命。     

Defect inspection of solder bumps using the scanning acoustic microscopy and fuzzy SVM algorithm

Flip chip technology has been extensively used in high density electronic packaging over the past decades. With the decrease of solder bumps in dimension and pitch, defect inspection of solder bumps becomes more and more challenging. In this paper, an intelligent diagnosis system using the scanning acoustic microscopy (SAM) is investigated, and the fuzzy support vector machine (F-SVM) algorithm is developed for solder bump recognition. In the F-SVM algorithm, we apply a fuzzy membership to input feature data so that the different input features can make different contributions to the learning procedure of the network. It solves the problem of feature data aliasing in the traditional SVM. The SAM image of flip chip is captured by using an ultrasonic transducer of 230 MHz. Then the segmentation of solder bumps is based on the gradient matrix of the original image, and the statistical features corresponding to every solder bump are extracted and adopted to the F-SVM network for solder bump classification and recognition. The experiment results show a high accuracy of solder defect recognition, therefore, the diagnosis system using the F-SVM algorithm is effective and feasible for solder bump defect inspection.     

分步电镀法制备Sn-Ag-In三元凸点及其可靠性

本文介绍了一种制备细节距、元素分布均匀的Sn-Ag-In三元凸点的方法。其特征在于在Cu凸点下金属层上分步电镀Sn-Ag和In,通过精确控制回流过程,获得了Sn1.8Ag9.4In凸点。研究发现位于Sn-Ag-In焊料和Cu之间的金属间化合物厚度随回流时间的延长而生长,这使得焊料基体中Ag相对浓度增加,因此在凝固过程中,更多的Ag2In相析出,起到了颗粒增强的作用。