Formation of polycrystalline-Si thin-film transistors with tunneling field-effect-transistor structure

The formation of a poly-Si thin-film transistor (TFT) device with a tunneling field-effect-transistor (TFET) structure has been studied. With scaling the gate length down to 1 μm, the poly-Si TFT device with a conventional metal-oxide-semiconductor-field-effect-transistor structure would be considerably degraded, which exhibits an off-state leakage of about 10 nA/μm at a drain bias of 6 V. The short channel effect would tend to cause the source/drain punch-through and also increase the lateral electric field within the channel region, thus enhancing the carried field emission via trap states. The TFET structure can be employed to alleviate the short channel effect in the poly-Si TFT device. As a result, even for a gate length of 1 μm, the poly-Si TFT device with the TFET structure can exhibit an off-state leakage smaller than 1 pA/μm and an on/off current ratio of about eight orders at a drain bias of 7 V. Furthermore, even for a gate length of only 0.2 μm, the resultant poly-Si TFT device with the TFET structure can exhibit good electrical characteristics with an off-state leakage smaller than 10 pA/µm and an on/off current ratio of about six orders at a drain bias of 3.2 V. As a result, this scheme is promising for implementing a high packing density of poly-Si TFT devices.     

Contact resistance variation in top-contact organic thin-film transistors with the deposition rate of Au source/drain electrodes

We investigated the effect of the deposition rate of Au source/drain electrodes on the contact resistance of the top-contact organic thin-film transistors (OTFTs). For the formation of source/drain contacts, Au was thermally deposited at the different rates of 0.5, 1.0, 5.0, and 13.0 Å/s. With increasing the Au deposition rate, the contact resistance extracted at the gate voltage of − 30 V could be reduced from 14 × 10⁶ to 2.4 × 10⁶ Ω, resulting in the characteristic improvements of the top-contact OTFT. It is also found that the contact resistance significantly affects the off-state currents of the device having the short channel length of 10 μm. The control of the deposition rate of source/drain electrodes is suggested to optimize the contact properties of the top-contact OTFTs as well as the device performance.     

Effect of layout arrangements on strained n-type metal-oxide-semiconductor field-effect transistors with silicon-carbon stressor

The stress evolution of n-type metal-oxide-semiconductor field-effect transistors with silicon-carbon stressor is systematically examined using three-dimensional finite element analysis. The effect of gate width dependence with a layout arrangement of dummy active of diffusion (OD) on device performance is also discussed. Results indicate that as a 1.0 μm gate width is adopted, a drain current enhancement of 26.19% could be achieved through an increase in tensile and compressive stress along the transport and vertical directions, respectively. However, the enhancement in device performance deteriorates from 22.02% to 15.98% as the gate width decreases from 1.0 μm to 0.1 μm. This phenomenon is attributed to the dependence of stress domination along the channel direction on the width dimensions of device gate. This study also finds that when a long dummy OD is used, the effect of length on performance improvement is enhanced for a device with a small OD.     

Organic thin film transistor using silver electrodes by the ink-jet printing technology

We have developed a conductive ink containing silver nanoparticles from which the electrodes for organic thin film transistor were directly patterned by ink-jet printing. Nano-sized silver particles having ∼ 20 nm diameter was used for a direct metal printing. Silver conductive ink was printed on the heavily doped n-type silicon wafer with 200-nm thick thermal SiO₂ layer as a substrate. To achieve a high line resolution and smooth conductive path, the printing conditions such as the inter-drop distance, stage moving velocity and temperature of the pre-heated substrates were optimized. After the heat-treatment at temperatures of 200 °C for 30 min, the printed silver patterns exhibit metal-like appearance and the conductivity. To fabricate a coplanar type TFTs, an active material of semiconducting oligomer, α,ω-dihexylquaterthiophene (DH4T) in a chlorobenzene was deposited between the ink-jet printed silver electrodes by drop casting. The OTFT with the ink-jetted source/drain electrodes shows general performance characteristics with good saturation behavior and no significant contact resistance as compared to the one with vacuum deposited electrodes. The electrical characteristic parameters of OTFT show the mobility of 1.3 × 10^− 3 cm² V^− 1 s^− 1 in the saturation regime, on/off current ratio over 10³, and threshold voltage of about − 13 V.     

Downscaling of self-aligned, all-printed polymer thin-film transistors

Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poor resolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages. Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100-400 nm. The use of a crosslinkable polymer gate dielectric with 30-50 nm thickness ensures that basic scaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistance effects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasitic overlap capacitance to values as low as 0.2-0.6 pF mm(-1), and allows transition frequencies of fT = 1.6 MHz to be reached. Our self-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, while remaining compatible with the requirements of large-area, flexible electronics manufacturing.     

The fabrication of front electrodes of Si solar cell by dispensing printing

The dispensing printing was applied to fabricate the front electrodes of silicon solar cell. In this method, a micro channel nozzle and normal Ag paste were employed. The aspect ratio and line width of electrodes could be controlled by the process variables such as the inner diameter of nozzle, dispensing speed, discharge pressure, and the gap between wafer and nozzle. For the nozzle with the inner diameter of 50 μm, the line width and aspect ratio of electrode were under 90 μm and more than ∼0.2, respectively. When comparing the efficiency of solar cell prepared by conventional screen printing and the dispensing printing, the latter exhibited 19.1%, which is 0.8% absolute higher than the former even with the same Ag paste. This is because the electrode by dispensing printing has uniform aspect ratio and narrow line width over the length of electrode.     

Fabrication of n-type Schottky barrier thin-film transistor with channel length and width of 0.1 μm and erbium silicide source/drain

In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, I_ON/I_OFF ratio of 5.8 × 10⁴ and I_ON of 2 μA/µm at V_G = 3 V, V_D = 2.5 V for 0.1 μm device. A process temperature is maintained at less than 600 °C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology.     

Preparation and soft lithographic printing of nano-sized ITO-dispersions for the manufacture of electrodes for TFTs

The production of printed electronics exhibits an enormous economical potential due to the possibility to manufacture innovative products at low cost. At the moment, one of the major challenges for the fabrication of printed electronics is the controllability of the material properties during processing and the miniaturization of the deposited structures. In this context, the application of soft lithographic techniques appears promising, because they allow a defined patterning of the materials in the range of few nanometers, which is far below the limits of other printing techniques like inkjet-printing or screen printing. This work proves the applicability of the soft lithographic technique micro-molding in capillaries (MIMIC) for the manufacture of conductive indium tin oxide (ITO) electrodes. For the creation of stable dispersions of ITO nano-sized particles, steric as well as electrostatic stabilization concepts are applied. The prepared dispersions are characterized with regard to the later processing via MIMIC. The geometry and the electrical properties of the soft lithographically deposited structures are determined to prove their functionality. Special attention is paid to the influence of the wetting behavior of the dispersions on the resulting geometry of the structures. Finally, the applicability of the optimized structures is demonstrated by the assembly of a thin film transistor (TFT), in which the deposited structures serve as source and drain electrodes.     

Characteristics of gravure printed InGaZnO thin films as an active channel layer in thin film transistors

Characteristics of oxide semiconductor thin film transistor prepared by gravure printing technique were studied. This device had inverted staggered structure of glass substrate/MoW/SiNx/ printed active layer. The active layer was printed with precursor of indium gallium zinc oxide solution and then annealed at 550 °C for 2 h. Influences of printing parameters (i.e. speed and force) were studied. As the gravure printing force was increased, the thickness of printed film was decreased and the refractive index of printed active layer was increased. The best printed result in our study was obtained with printing speed of 0.4 m/s, printing force of 400 N and the thickness of printed active layer was 45 nm. According to AFM image, surface of printed active layer was quite smooth and the root-mean square roughness was approximately 0.5 nm. Gravure printed active layer had a field-effect mobility of 0.81 cm²/Vs and an on-off current ratio was 1.36 × 10⁶.     

The characteristics of sub-10 nm gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors

10 and 6 nm erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) were manufactured. The manufactured 10 nm n-type SB-MOSFET showed a large on/off current ratio (> 10⁶) with low leakage current less than 10^− 5 μA/μm due to the existence of the robust Schottky barrier between source and channel region. The saturation currents were 550 and 320 μA/μm when drain and gate voltages were 2 V and 3 V, for the 10 and 6 nm erbium-silicided n-type SB-MOSFETs, respectively. The manufactured SB-MOSFETs exhibited superior short channel characteristics due to the existence of Schottky barrier between source and channel region.     

Formation of polycrystalline thin-film transistors with stacked poly-SiGe/poly-Si channel layer for low-voltage applications

A thin-film transistor (TFT) with polycrystalline SiGe/Si stacked channel layer has been proposed for low-voltage applications. For the stacked poly-SiGe/poly-Si channel layer, the resultant 1-μm TFT device can achieve an on/off current ratio above 7 orders and a relatively large on-state current at a low operating voltage, and also cause better transfer characteristics than both the conventional poly-Si and poly-SiGe channel layers. As compared to the poly-Si channel layer, the poly-SiGe channel layer may cause a larger on-state current at a small gate bias of 3 V, due to smaller difference between conduction band and intrinsic level. However, even at a small drain bias of 3 V, the poly-SiGe channel layer leads to an off-state leakage current of about 2 order larger than the poly-Si channel layer, since a smaller energy bandgap may cause more carrier field emission via trap states. As a result, when a poly-SiGe/poly-Si stacked channel layer is employed, the leakage current may be suppressed to a low level as that for the poly-Si channel layer, and the resultant on-state current at a low gate bias voltage can be close to a relatively high level as that for the poly-SiGe channel layer.     

An investigation of contact resistance between metal electrodes and amorphous gallium-indium-zinc oxide (a-GIZO) thin-film transistors

This paper reports our investigation of different source/drain (S/D) electrode materials in thin-film transistors (TFTs) based on an indium-gallium-zinc oxide (IGZO) semiconductor. Transfer length, contact resistance, channel conductance, and effective resistances between S/D electrodes and amorphous IGZO thin-film transistors were examined. Intrinsic TFT parameters were extracted by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low drain voltage. The TFTs fabricated with Cu S/D electrodes showed the lowest contact resistance and transfer length indicating good ohmic characteristics, and good transfer characteristics with intrinsic field-effect mobility (μ_FE-i) of 10.0 cm²/Vs.     

Graphene-like metal-on-silicon field-effect transistor

This paper presents a field-effect transistor with a channel consisting of a two-dimensional electron gas located at the interface between an ultrathin metallic film of Ni and a p-type Si(111) substrate. The gate length is L = 2 μm, its width is W = 180 μm, and the source-drain separation is 188 μm, the role of the gate dielectric being played by the surface states of the ultrathin metal layer. We have demonstrated that the two-dimensional electron gas channel is modulated by the gate voltage. The dependence of the drain current on the drain voltage has no saturation region, similar to a field-effect transistor based on graphene. The drain current is 2 mA at a drain voltage of 3 V and a gate voltage of 1.07 V, while the transconductance is 0.6 mS for a drain voltage of 6 V and a gate voltage of 1 V. However, the transport in this transistor is not ambipolar, as in graphene, but unipolar.     

Characteristics of sputtered Al-doped ZnO films for transparent electrodes of organic thin-film transistor

Aluminum-doped ZnO (AZO) thin-films were deposited with various RF powers at room temperature by radio frequency (RF) magnetron sputtering method. The electrical properties of the AZO film were improved with the increasing RF power. These results can be explained by the improvement of the crystallinity in the AZO film. We fabricated the organic thin-film transistor (OTFT) of the bottom gate structure using pentacene active and poly-4-vinyl phenol gate dielectric layers on the indium tin oxide gate electrode, and estimated the device properties of the OTFTs including drain current-drain voltage (I_D-V_D), drain current-gate voltage (I_D-V_G), threshold voltage (V_T), on/off ratio and field effect mobility. The AZO film that grown at 160 W RF power exhibited low resistivity (1.54 × 10^− 3 Ω·cm), high crystallinity and uniform surface morphology. The pentacene thin-film transistor using the AZO film that's fabricated at 160 W RF power exhibited good device performance such as the mobility of 0.94 cm²/V s and the on/off ratio of ~ 10⁵. Consequently, the performance of the OTFT such as larger field-effect carrier mobility was determined the conductivity of the AZO source/drain (S/D) electrode. AZO films prepared at room temperature by the sputtering method are suitable for the S/D electrodes in the OTFTs.     

Formulation and screen printing of water based conductive flake silver pastes onto green ceramic tapes for electronic applications

Environmentally friendly, water-based silver pastes, adapted for screen printing, were formulated with different silver contents (67–75%). These pastes allowed screen printing onto low temperature co-fired ceramic (LTCC) of narrow conductive tracks with a 60 μm line width and a 3 × 10⁻⁸ Ω m electrical resistivity. Inks were formulated with a mixture of spherical and flake shape silver particles with 2–4 μm mean diameter. Rheological behaviour of pastes was studied in order to determine its effect on printed lines properties. Prepared inks were then screen printed and sintered under normal atmosphere at 875 °C. As expected, electrical properties depended on silver content. Resistivity values varying from 1.6 × 10⁻⁸ to 3.3 × 10⁻⁸ Ω m were calculated over 36.3 cm line length. These values are very close to bulk silver resistivity (1.6 × 10⁻⁸ Ω m). Compared to previous research and commercial pastes, the newly formulated pastes reached equivalent or even better conductivities with lower silver content (70% by weight).     

Electrical behavior of p-type PbS-based metal-oxide-semiconductor thin film transistors

Chemically deposited lead sulfide (PbS) thin films were used as the semiconductor active layer in common-gated thin film transistors. The PbS films were deposited at room temperature on SiO₂/Si-p wafers. Lift-off was used to define source and drain contacts (gold, Au) on top of the PbS layer with channel lengths ranging from 10 to 80 μm. The Si-p wafer with a back chromium-gold contact served as the common gate for the transistors. Experimental results show that as-deposited PbS are p-type in character and the devices exhibit typical drain current versus source-drain voltage (I_DS-V_DS) behavior as a function of gate voltage. The values of threshold voltage of the devices were in the range from −7.8 to 1.0 V, depending on the channel length. Channel mobility was approximately 10^− 4 cm²V^− 1 s^− 1. The low channel mobility in the devices is attributed to the influence of the microstructure of the nanocrystalline thin films. The electrical performance of the PbS-based devices was improved by thermal annealing the devices in forming gas at 250 °C. In particular, channel mobility increased and threshold voltage decreased as a consequence of the thermal annealing.     

Selective growth of ZnO nanorods for gas sensors using ink-jet printing and hydrothermal processes

Selective growth of ZnO nanorod arrays with well-defined areas was developed to fabricate the NO₂ gas sensor. The seed solution was ink-jet printed on the interdigitated electrodes. Then, vertically aligned ZnO nanorods were grown on the patterned seed layer by the hydrothermal approach. The influences of seed-solution properties and the ink-jet printing parameters on the printing performance and the morphology of the nanorods were studied. Round micropattern (diameter: 650 μm) of ZnO nanorod arrays is demonstrated. The dimensions and positions of the nanorod arrays can be controlled by changing the printed seed pattern. The effects of nanorod structure and nanorod size on the gas-sensing capability of ZnO nanorod gas sensors were demonstrated. Due to the high surface-to-volume ratios of the nanorod-array structure, the ZnO nanorod gas sensor can respond to 750 ppb NO₂ at 100 °C. The sensors without baking treatment exhibit the typical response of a p-type semiconductor. However, only the response of n-type semiconductor oxides was observed after the annealing treatment at 150 °C for 2 h.     

Electrostatics of nanowire transistors

The electrostatics of nanowire transistors are studied by solving the Poisson equation self-consistently with the equilibrium carrier statistics of the nanowire. For a one-dimensional, intrinsic nanowire channel, charge transfer from the metal contacts is important. We examine how the charge transfer depends on the insulator and the metal/semiconductor Schottky barrier height. We also show that charge density on the nanowire is a sensitive function of the contact geometry. For a nanowire transistor with large gate underlaps, charge transferred from bulk electrodes can effectively "dope" the intrinsic, ungated region and allow the transistor to operate. Reducing the gate oxide thickness and the source/drain contact size decreases the length by which the source/drain electric field penetrates into the channel, thereby, improving the transistor characteristics.     

Charge control in a model biphenyl molecular transistor

We study charge control in a gated 4,4'-biphenyl diradical molecular transistor using ab initio density functional theory calculations. I-V curves and intrinsic gate capacitances were derived. We find charge control in this transistor to be strongly affected by polarization of the sigma-states of the molecule, leading to strong electrostatic coupling of the internal potentials to the source and drain electrodes, and relatively weak coupling to the gate. We suggest that this spatially dependent and anisotropic polarization is an essential element in the operation of molecular transistors.