Testing content addressable memories with physical fault models

the effectiveness and efficiency of the proposed physical fault models and algorithms.     

Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits

We first study the impacts of soft errors on various types of CAM for different feature sizes. After presenting a soft error immune CAM cell, SSB-RCAM, we propose two kinds of reliable CAM, DCF-RCAM and DCK-RCAM.In addition, we present an ignore mechanism to protect dual cell redundancy CAMs against soft errors. Experimental results indicate that the 11T-NOR CAM cell has an advantage in soft error immunity. Based on 11T-NOR, the proposed reliable CAMs reduce the SER by about 81% on average with acceptable overheads. The SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.     

降低亚100nm CAM电路的软错误易感性

电路的软错误易感性是VLSI设计中需要考虑的重要问题。CAM广泛应用于各种片上结构中,非常容易受软错误感染。然而,CAM的保护比其它存储元件难度更大。本文首先研究了软错误对不同类型、不同特征尺寸CAM的影响。在介绍一种软错误免疫CAM单元SSB-RCAM后,提出两种可靠CAM DCF-RCAM和DCK-RCAM。此外,本文还提出一种抛弃机制保护双单元冗余CAM免受软错误的影响。实验结果表明,11T-NOR结构的CAM单元在软错误免疫性上具有优势。基于11T-NOR结构,所提出的可靠CAM结构在可接受的开销下,平均可降低约81%的软错误率。在特定的应用中,还可以通过使用抛弃机制降低双单元冗余CAM的软错误率。     

Low-power content addressable memory design using two-layer P-N match-line control and sensing

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs.     

OpenFlow table lookup scheme integrating multiple-cell Hash table with TCAM

In OpenFlow networks,switches accept flow rules through standardized interfaces,and perform flow-based packet processing.To facilitate the lookup of flow tables,TCAM has been widely used in OpenFlow switches.However,TCAM is expensive and consumes a large amount of power.A hybrid lookup scheme integrating multiple-cell Hash table with TCAM was proposed for flow table matching to simultaneously reduce the cost and power consumption of lookup structure without sacrificing the lookup performance.By theoretical analysis and extensive experiments,optimal capacity configuration of Hash table and TCAM was achieved with the optimized cost of flow table lookup.The experiment results also show that the proposed lookup scheme can save over 90% cost and the power consumption of flow table matching can be reduced significantly compared with the pure TCAM scheme while keeping the similar lookup performance.     

Testing and Diagnosis Methodologies for Embedded Content Addressable Memories

Embedded content addressable memories (CAMs) are important components in many system chips where most CAMs are customized and have wide words. This poses challenges on testing and diagnosis. In this paper two efficient March-like test algorithms are proposed first. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N × W-bit CAM. The second algorithm uses 3N log₂ W Write and 2W log₂ W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. We also present the algorithms that can locate the cells with comparison faults. Finally, a CAM BIST design is briefly described.     

微处理器系统功能测试

针对微处理器系统测试问题，提出了一种全新的功能测试方法。详细介绍了该方法的硬件组成和测试生成。该方法以结构故障模型为基础，将数字电路故障分为3大类6种故障，分另4为固定型故障、开路型故障和短路型故障3种，其中固定型故障又可分为固定0和固定1两种，开路故障分为开路为0、开路为1以及开路为Z三种。为了验证该方法的有效性，本文针对一块以MC6800为微处理器的电路板进行了测试程序开发。实验结果表明，故障覆盖率取得了满意的结果。     

FeW的差分故障攻击

为了评估轻量级分组密码算法FeW的安全性,提出并讨论了一种针对FeW算法的差分故障攻击方法。该方法采用单字节随机故障模型,选择在FeW算法的最后一轮右侧引入单字节随机故障,利用线性扩散函数的特点获取差分信息,并基于S盒差分分布统计规律实现密钥恢复。实验结果表明,平均47.73次和79.55次故障注入可以分别完全恢复FeW-64-80和FeW-64-128的主密钥,若在恢复密钥过程中加入2¹⁰的穷举计算,所需平均故障注入次数分别降至24.90和41.50。该方法可以有效地攻击FeW算法。     

Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation

This paper presents a new algorithm for the generation of test sequences for finite state machines. Test sequence generation is based on the transition fault model, and the generation of state-pair distinguishing sequences. We show that the use of state-pair distinguishing sequences generated from a fault-free finite state machine will remain a distinguishing sequence even in the presence of a single transition fault, thus guaranteeing complete single transition fault coverage. Analysis and experimental results show that the complexity of the test sequence generation algorithm is less than those of the previous algorithms. The utility of the transition fault model, and the generated test sequences is shown by their application to sequential logic circuits. These results show more than a factor of 10 improvement in the test generation time and some reduction in test length while maintaining 100% transition fault coverage.Now with Intel Corporation, FM5-161, 1900 Prairie City Road, Folsom, CA 95630.Now with Chrysalis Symbolic Design, 101 Billerica Ave., North Billerica, MA 01862.     

基于FastICA算法的电路故障诊断方法

在电路故障检测中针对元件种类较少且同一种元件重复出现的电路,提出基于FastICA(fast independent component analysis)算法的故障诊断方法。该方法首先对电路中的元件进行分类再按信号叠加算法分组建立测试电路,电路正常工作时测试电路不给电。利用FastICA算法对测试信号进行盲分离,初步判断分离结果后与预先建立的元件故障信号库Mf的信号作相关分析判定故障类型。这种故障诊断方法简单易实现且对元件类型没有限制,在检测过程中元件之间没有相互干扰可确保诊断的准确性。仿真表明该方法能有效判断出电路的故障情况。     

Improvement Differential fault attack on TWINE

A new method of differential fault attack was proposed,which was based on the nibble-group differential diffusion property of the lightweight block cipher TWINE.On the basis of the statistical regularity of the S-box differential distribution,the lower bound of the probability of recovering round key was calculated.Then expectation of number of fault injections when restoring seed key can be estimated.Theoretical proof and experimental results both show that an average of nine times of fault injections in 33,34 and 35 rounds bring about the seed key recovered completely.Finally,the improvement of the fault injection location was proposed,which enhances the feasibility of the genuine attack.     

系统级故障诊断的研究现状与发展前景

随着大数据时代的到来,人们对于计算机系统的稳定性要求日益增高,如何快速而准确地找出系统中的故障点,成为了人们的研究热题,对系统级故障诊断算法的研究逐渐受到了人们的重视。本文首先对现有的系统级故障诊断算法进行了分类,进而阐述了系统级故障诊断算法的近期主要研究成果,最后预测了该领域的未来研究方向与发展前景。     

March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories

A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper.     

Fault Models and Test Procedures for Flash Memory Disturbances

Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.     

MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.     

On-Chip SRAM内建自测试及其算法的研究

具体研究on-Chip SRAM的内建自测试及其算法.在引入嵌入式存储器内建自测试的基础上,详细分析on-Chip SRAM内建自测试的具体实现方法,反映出内建自测试对于简化测试程序和缩短测试时间,从而降低测试成本的重要性.详细描述在测试on-Chip SRAM时常用的算法,并具体分析非传统性测试算法——Hammer算法和Retention算法.     

边界扫描在带DSP芯片数字电路板测试中的应用

为了解决带DSP（数字信号处理器）芯片数字电路板中部分非边界扫描器件的功能测试难题,采用了边界扫描测试技术与传统的外部输入矢量测试相结合的方法,对一块带有DSP芯片数字电路板中的非边界扫描器件进行了功能测试。测试结果表明,该测试方法能够对这部分器件进行有效的故障检测和故障隔离,并可将故障隔离到芯片。充分说明这种应用边界扫描技术与传统测试方法相结合的功能测试方法能够有效地解决带DSP芯片数字电路板中部分非边界扫描器件的功能测试问题。     

基于内容分析的短信种子客户挖掘模型与算法

为从海量的短信记录中挖掘短信种子客户,控制种子短信的传播路径,提高其传播效率,提出了一种基于内容分析的短信种子客户挖掘模型与算法.首先通过分析客户转发短信的兴趣性、随机性、单向性特征,构建客户转发短信的树型模型;其次,通过定义和应用综合评价函数生成优化的种子客户挖掘模型,并基于亲密群概念实现短信种子客户的挖掘;最后,使用电信运营商的实际数据进行实证分析,验证了上述模型与算法的有效性.     

An Effective Test and Diagnosis Algorithm for Dual‐Port Memories

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual‐port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual‐port memories.     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.