Light emission near 1.3 /spl mu/m using ITO-Al/sub 2/O/sub 3/-Si/sub 0.3/Ge/sub 0.7/-Si tunnel diodes

We have fabricated Sn : In/sub 2/O/sub 3/ (ITO)-Al/sub 2/O/sub 3/ dielectric on Si/sub 1-x/Ge/sub x/-Si metal-oxide-semiconductor tunnel diodes which emit light at around 1.3 /spl mu/m, for x=0.7. The emitted photon energy is smaller than the bandgap energy of Si, thus, avoiding strong light absorption by the Si substrate. The optical device structure is compatible with that of a metal-oxide-semiconductor field-effect transistor, since a conventional doped poly-Si gate electrode will be transparent to the emitted light. Increasing the Ge composition from 0.3 to 0.4 only slightly decreases the light-emitting efficiency.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Effect of Mg doping on the superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta//

Superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// (Cu/sub 1-x/Tl/sub x/Mg/sub y/-1234) material have been studied in the composition range y=0,1.5,2.25. The zero resistivity critical temperature [T/sub c/(R=0)] was found to increase with the increased concentration of Mg in the unit cell; for y=1.5 [T/sub c/(R=0)]=131 K was achieved which is hitherto highest in Cu/sub 1-x/Tl/sub x/-based superconductors. The X-ray diffraction analyses have shown the formation of a predominant single phase of Cu/sub 0.5/Tl/sub 0.5/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// superconductor with an inclusion of impurity phase. It is observed from the convex shape of the resistivity versus temperature measurements that our as-prepared material was in the region of carrier over-doping, and the number of carriers was optimized by postannealing experiments in air at 400/spl deg/C, 500/spl deg/C, and 600/spl deg/C. The T/sub c/(R=0) was found to increase with postannealing and the best postannealing temperature was found to be 600/spl deg/C. The mechanism of increased T/sub c/(R=0) is understood by carrying out infrared absorption measurements. It was observed through softening of Cu(2)-O/sub A/-Tl apical oxygen mode that improved interplane coupling was a possible source of enhancement of T/sub c/(R=0) to 131 K.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate

In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.     

The thermal stability of one-transistor ferroelectric memory with Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-poly-SiO/sub 2/-Si gate stack

The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-Poly-SiO/sub 2/-Si was characterized in the temperature range of -10/spl deg/C to 150/spl deg/C. The memory windows decrease when the temperatures are higher than 60/spl deg/C. The drain currents (I/sub D/) after programming to on state decrease with increasing temperature. The drain currents (I/sub D/) after programming to off state increase with increasing temperature. The ratio of drain current (I/sub D/) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150/spl deg/C. On the other hand, the memory window and the ratio of I/sub D/(on)/I/sub D/(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10/spl deg/C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60/spl deg/C.     

On the threshold Voltage of strained-Si-Si/sub 1-x/Ge/sub x/ MOSFETs

The threshold voltage shifts (/spl Delta/V/sub t(SS)/ relative to V/sub t/ of Si-control devices) in strained-Si-Si/sub 1-x/Ge/sub x/ (SS) CMOS devices are carefully examined in terms of the shifted two-dimensional energy subbands and the modified effective conduction- and valance-band densities of states. Increased electron affinity as well as bandgap narrowing in the SS layer are shown to be the predominant components of /spl Delta/V/sub t(SS)/, whereas the density-of-state terms tend to be relatively small but not insignificant. The study reveals, for both n-channel and p-channel SS MOSFETs, important physical insights on the varied surface potential at threshold, defined by energy quantization as well as the strain, and on the shifted flat-band voltage that is also part of /spl Delta/V/sub t(SS)/. Models for /spl Delta/V/sub t(SS)/ dependent on the Ge content (x), with comparisons to published data, are presented and used to show that redesign of channel doping in the SS nMOSFET to increase the significantly reduced V/sub tn(SS)/ for off-state current control tends to substantively diminish the inherent SS CMOS relative speed enhancement, e.g., by more than 40% for x=0.20. Interestingly, the SS pMOSFET model predicts small increases in the magnitude of V/sub tp(SS)/.     

BV/sub CEO/--BV/sub CBO/ separation and sharpness of breakdown in high-speed bipolar transistors

The effect of secondary impact ionization by the noninitiating carrier on the near avalanche behavior of high-speed n-p-n bipolar transistors is studied. We show that secondary collector ionization by generated holes traveling back toward the base layer significantly reduces BV/sub CBO/ if the hole ionization coefficient is higher than that of electrons [/spl beta//sub p/(E)>/spl alpha//sub n/(E)]: positive feedback associated with a strong secondary ionization sharpens the breakdown characteristic by speeding up carrier multiplication and decreases separation between the open-base collector-emitter (BV/sub CEO/) and the open-emitter base-collector (BV/sub CBO/) breakdown voltages. The effect of secondary ionization on the BV/sub CEO/-BV/sub CBO/ separation has not previously been described. Multiplication coefficient comparisons for representative InP, GaAs, and Si collectors indicate all structures can sustain low-current above BV/sub CEO/ operation from a transport (nonthermal) point of view, although the different degrees of secondary ionization in various semiconductors lead to fundamental differences when InP is compared to GaAs and Si since for the latter materials /spl beta//sub p/(E)相似文献   

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Al/sub 2/O/sub 3/-Ge-on-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates

High-/spl kappa/ Al/sub 2/O/sub 3//Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the Al/sub 2/O/sub 3/-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with Al/sub 2/O/sub 3/-Si MOSFETs. Additionally, Al/sub 2/O/sub 3/-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than Al/sub 2/O/sub 3/-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500/spl deg/C rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-/spl kappa/ to minimize interfacial reactions and crystallization of the high-/spl kappa/ material, and oxygen penetration in high-/spl kappa/ MOSFETs.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.