Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks

Multi-processor systems need interconnection networks (INs) in order to make the connection among the processors, memory modules, and nodes. Bus interconnection network is the simplest and least expensive one among all the INs. Therefore, bus network is easily understood and preferred by manufactures for implementation. However, a bus network is inherently a non-fault tolerant and blocking network. To cope with these problems, a solution is to use several buses in parallel on a network. Based on this idea, various schemes can be designed for a bus network: (1) Multiple-bus with full bus-memory connection, (2) Multiple-bus with single bus-memory connection, (3) Multiple-bus with partial bus-memory connection, and (4) Multiple-bus with class-based memory connection. On the other hand, a metric for the efficiency of fault-tolerant systems is its reliability. Although, there is no detailed analysis of the reliability of bus-based networks, this paper presents accurate and complete reliability analysis of bus-based networks to achieve these aims: (1) Determining the most efficient design of bus-based networks in terms of reliability, cost-effectiveness, and blocking issues, (2) Providing new methods for evaluating the performance of bus-based networks.     

Decomposition in Reliability Analysis of Fault-Tolerant Systems

Two important problems which arise in modeling fault-tolerant systems with ultra-high reliability requirements are discussed. 1) Any analytic model of such a system has a large number of states, making the solution computationally intractable. This leads to the need for decomposition techniques. 2) The common assumption of exponential holding times in the states is intolerable while modeling such systems. Approaches to solving this problem are reviewed. A major notion described in the attempt to deal with reliability models with a large number of states is that of behavioral decomposition followed by aggregation. Models of the fault-handling processes are either semi-Markov or simulative in nature, thus removing the usual restrictions of exponential holding times within the coverage model. The aggregate fault-occurrence model is a non-homogeneous Markov chain, thus allowing the times to failure to possess Weibull-like distributions. There are several potential sources of error in this approach to reliability modeling. The decomposition/aggregation process involves the error in estimating the transition parameters. The numerical integration involves discretization and round-off errors. Analysis of these errors and questions of sensitivity of the output (R(t)) to the inputs (failure rates and recovery model parameters) and to the initial system state acquire extreme importance when dealing with ultra-high reliability requirements.     

Reliability Modeling and Analysis of Fault-Tolerant Memories

A memory array reliability model is developed that can be applied to a wide range of memory organizations including random-access memories (RAM) and read-only memories (ROM). The model is particularly useful for computing the reliability of fault-tolerant memories that employ techniques such as hardware redundancy, error-correcting codes, and software error-correcting algorithms. The model accommodates the effect of faults masked by data. Reliability models that incorporate the array model are given for a simplex RAM, an N-modular-redundant RAM, a spared RAM, a single-error-correcting RAM, a multiple-error-correcting RAM, and a ROM. Reliability characteristics of these memories are compared. The results suggest that memories with error-correcting capability and spare bit-planes provide the best reliability. Memories with sparing at the array level are next best followed by NMR and simplex organizations. ROM reliability is shown to be more optimistic when masked faults are considered.     

Performance/Reliability Measures for Fault-Tolerant Computing Systems

Some fault-tolerant computing systems are discussed and existing reliability measures are explained. Some performance/reliability measures are introduced. Several systems are compared by using numerical examples with the new measures.     

Reliability & Safety Analysis of a Fault-Tolerant Controller

This paper analyzes a fault-tolerant, microprocessor-based controller for an electric wheelchair. Two candidate architectures are considered, including reconfigurable duplication and stand-by sparing. The difference in the reliability and safety of the two candidates is determined through the use of Markov models. Safety is paramount in the wheelchair application because of the need to protect the physically disabled wheelchair user;reliability by itself is insufficient for selecting an appropriate architecture in this application. The results show that reconfigurable duplication is safer than standby sparing even though standby sparing is more reliable. Because of the better safety, reconfigurable duplication is the preferred approach for the wheelchair application. Safety is extremely important in the selection of a fault-tolerant architecture for the electric wheelchair control system. Standby sparing provides a conceptually simple approach that achieves a higher reliability than reconfigurable duplication. However, reconfigurable duplication has a higher safety for a given fault coverage. Because of the need for safety in the electric wheelchair control system, reconfigurable duplication is the selected approach.     

RPR容错功能的可靠性分析

采用"网络连通率"作为度量网络可靠性的参数,通过对系统模型的数学解析,建立了具有源路由功能和回绕功能的弹性分组环的可靠性数学模型。通过数值分析,得出了环处理器故障率对系统可靠性的影响。     

Fault-Tolerant ICs: The Reliability of TMR Yield-Enhanced ICs

The use of triple modular redundancy (TMR) for reliability enhancement is well known. This paper presents a simple method' for predicting the reliability of integrated circuits (ICs) which use TMR for yield enhancement. A simple yield-model is included as it is necessary to factor in the effect of consumption of redundancy paths due to wafer fabrication defects. TMR implementation is briefly discussed as well.     

双环双容错功能局域网的可靠性分析

采用“平均有效终端数”作为度量网络可靠性的参数，通过对系统模型的数学解析，建立了具有旁路和环路回接双容错功能的双环局域网(LAN)的可靠性数学模型。通过数值例，考察了网络结构因素对系统可靠性的影响，得到了最佳实际终端数存在的结论。     

SFTMP——一个实现软件容错的多处理机系统

多版本软件通过设计相异性实现了软件容错。为了对这种方法进行研究，我们的课题实现了一个三版本软件系统，称之为SFTMP（SoftwareFault－TolerantMultiProcessor）。本文描述了SFTMP的硬件结构和软件执行支持环境，该环境包括同步、表决和监控功能、版本间的通讯及故障的恢复和重构。     

容错计算机系统的可靠性建模和分布式仿真

对容错计算机系统的可靠性进行评估是一项重要而困难的工作。为容错计算机系统的各个组成部件建立了部件级故障模型,并以此为基础建立了整个容错计算机系统的可靠性测评模型。基于所建立模型,我们提出了分布式仿真的思想,它把系统的各个部件仿真为网络上的一个站点,并增设一台服务器来对整个系统的可靠性性能进行统计和分析。仿真结果验证了建立模型的正确性和方法的有效性。     

Availability Analysis of a Fault-Tolerant Computer System

Queueing network theory is applied in order to determine the availability of a fault-tolerant multiprocessor computer system. Mean repair times and utilizations of system units are computed. Subsystem availabilities are obtained by the decomposition technique of queueing network theory.     

容错轮询系统分析模型

本文提出的多服务器轮询系统分析模型考虑了故障对系统性能的影响,特别适应于在任务级或传输子系统级评估分布式实时系统的响应特性,对容错分布式系统设计及系统重组策略的优化、选择具有指导意义。     

Fault-Tolerant System Using 3-Value Logic Circuits

A ternary decision circuit implemented in CMOS technology is proposed. It can be used in a duplex binary fault-tolerant system to replace both the matcher and the switch circuit. The resultant system is simpler than the conventional one. The reliable design of the ternary decision circuit is discussed in detail. A duplex 2-of-3-value fault-tolerant system can be formed by two 2-of-3-value processors and a TDC. This system is more powerful than a duplex binary system since it can provide automatic error correcting function for certain faults. All single faults can be divided into self-checked faults and secure faults. For any self-checked faults, the TDC is self-testing, strongly fault secure, and totally self-checking. For any secure faults, the TDC is strongly fault secure.     

中兴MVC3000会议电视系统

文章在简介会议电视原理及组网的基础上,详述了中兴MVC3000会议电视系统技术,并举出组网实例。     

BDI3000在嵌入式系统调试中的应用

本文使用先进的嵌入式调试工具BDI 3000在GDB下实现嵌入式系统的调试,分别详细介绍了BDI3000与GDB的使用配置及注意事项,并结合PXA 270和PowerPC405处理器进行具体分析和实现,为处理器的进一步开发奠定了良好基础。     

Fault-Tolerant Software

Limitations in the current capabilities for verifying programs by formal proof or by exhaustive testing have led to the investigation of fault-tolerance techniques for applications where the consequence of failure is particularly severe. Two current approaches, N-version programming and the recovery block, are described. A critical feature in the latter is the acceptance test, and a number of useful techniques for constructing these are presented. A system model for the recovery block is introduced, and conclusions derived from this model that affect the design of fault-tolerant software are discussed.     

Passive Fault-Tolerant Control Design for Near-Space Hypersonic Vehicle Dynamical System

In this paper, an observer-based passive fault-tolerant control (FTC) scheme is proposed for a near-space hypersonic vehicle (NSHV) dynamical system with both parameter uncertainty and actuator faults. The parameter uncertainty is assumed to be norm-bounded, and the possible fault of each actuator is described by a variable varying within a given interval. Our aim is to design an observer-based FTC law such that, for the admissible parameter uncertainty and possible actuator faults, the resulting closed-loop system is asymptotically stable with a given disturbance attenuation level γ. The unknown gain matrices are characterized in terms of the solutions to some linear matrix inequalities (LMIs) which can be readily solved using standard software packages. The FTC scheme presented in this study is finally demonstrated via simulation on a linearized NSHV dynamical system to illustrate the effectiveness.     

大洋3000-LE非线性编辑系统的升级实践

在充分利用原设备系统各部件基础上,通过有限的经济投入和系统升级的方法,大幅度优化和提高广电设备系统性能,使得这些系统继续为广播电视事业发挥作用。本文以大洋3000-LE非线性编辑系统升级实践为例,具体介绍了计算机系统升级的一般过程和常用的一些处理方法。     

三取二架构容错计算机总线设计

主要分析了三取二架构的容错计算机内部通信通道需求,选择了满足需求的VME总线和基于RS-422标准的HDLC（高级数据链路控制协议）串行链路总线,并针对系统需求对总线进行了裁减和多连接冗余设计,分析了在三取二架构容错计算机中各总线应用的流程及其性能。     

容错计算机系统中潜在故障的分析和处理途径

潜在故障是容错系统的潜在危害，因为大多数容错系统是基于单故障假设。以汽车导航系统为例来研究这一潜在危害，并用马尔可夫模型说明潜在故障恶化系统平均故障前时间。本文深入研究了一些可能的补救措施，其中透明的在线测试是最有效的方法之一，而用暂时离线的热贮备系统进行测试则是更可靠的方法。