功率模块铜线键合技术及其可靠性研究

由于铝线键合逐渐不能满足如今功率模块功率密度、工作温度不断提升的可靠性要求,因此采用铜线代替铝线,以实现更高的可靠性工作寿命。对比分析了铜线、铝线键合工艺的特点、结合强度和可靠性,证明了铜线键合工艺的可行性和高可靠性。同时分析了铜线键合工艺目前存在的问题和应对措施。     

分立器件铜线的键合特点及其工艺研究

对铜线键合的优缺点及分立器件的结构特点进行了具体分析。根据分析结果,并结合具体的实验,给出了键合工艺条件和工艺参数对分立器件铜线键合过程的影响。此研究对提高分立器件铜线键合产品的质量及可靠性具有重要意义。     

铜键合线的发展与面临的挑战

介绍了当今微电子封装中重点关注的铜键合引线,指出了铜键合线的优缺点.铜线键合是一种代替金和铝键合的键合技术,人们关注它不仅因为它的价格成本优势,更由于铜线特有的机械和电学等方面的优良性能,当然,铜线键合技术还存在不少问题和挑战,针对这些存在的问题,进行了简要的介绍并提出相应的解决办法.     

DBC铜线键合工艺参数研究

铜线作为最有发展潜力的新一代键合材料,与铝线相比,具有优异的导电及导热能力。因绝缘栅双极型晶体管（IGBT）需承载大电流,采用铜线可在键合线数量不变的基础上提高电流传输能力和散热能力。采用铜线超声楔形键合对覆铜陶瓷基板（DBC）第一键合点和第二键合点的键合工艺参数进行研究,以剪切力作为衡量键合质量的标准,采用单因素分析法研究各参数对键合点强度的影响,采用正交试验确定最佳工艺参数,为铜线键合工艺的参数设定提供参考及指导方法。     

铜线键合Cu/Al界面金属间化合物微结构研究

由于铜线具有较高的热导率、卓越的电学性能以及较低的成本,被普遍认为将逐渐代替传统的金线而在IC封装的键合工艺中得到广泛的应用。铜线键合工艺中Cu/Al界面金属间化合物(IMC)与金线键合的Au/Al IMC生长情况有很大差别,本文针对球焊键合中键合点的Cu/Al界面,将金属间化合物生长理论与分析手段相结合,研究了Cu/Al界面IMC的生长行为及其微结构。文中采用SEM测试方法,观察了IMC的形貌特点,测量并得到了IMC厚度平方正比于热处理时间的关系,计算得到了生长速率和活化能数值,并采用TEM,EDS等测试手段,进一步研究了IMC界面的微结构、成分分布及其金相结构。     

铜线键合技术的发展与挑战

铜线键合技术近年来发展迅速,超细间距引线键合是目前铜线键合的主要发展趋势.介绍了铜线键合的防氧化措施以及键合参数的优化,并从IMC生长及焊盘铝挤出方面阐述了铜线键合的可靠性机理.针对铜线在超细间距引线键合中面临的问题,介绍了可解决这些问题的镀钯铜线的性能,并阐述了铜线的成弧能力及面临的挑战.     

铜线键合的抗氧化技术研究

在铜线键合的过程中通入惰性保护气体,或在纯铜线表面涂覆金属钯防氧化层都可以改善铜线键合的抗氧化性能。为了评价上述两种方法对铜线键合抗氧化性能的改进情况,使用先进的材料表征方法分析不同保护气体流量情况下键合形成的金属熔球的形貌,金属熔球表面的氧原子数分数和表面氧化层的厚度。研究表明,保护气体流量为0.51 L/min时,可以在保证成本较低的情况下获得最佳的抗氧化效果。通过XPS和TEM分析发现,铜线表面涂覆金属钯可以延长铜线的存储寿命,降低键合界面的氧含量,提高键合的可靠性。     

键合功率对银线键合质量的影响

铜线键合技术是半导体封装的关键技术之一,影响键合质量的因素有很多。本文基于热压超声键合的方法,对影响铜线键合质量的主要工艺参数——键合功率,进行DOE研究分析。通过对键合后的产品进行焊点剪切失效模式、拉伸失效模式以及弹坑实验分析,研究键合功率对键合质量的影响,进而确定合理的工艺参数,最终应用于大批量生产。     

浅谈镀钯铜线的特性

随着金线价格一路上涨并创下历史新高,大型封装厂正在加大对铜线制程的投入。通过封装厂多年的摸索,发现镀钯铜线是金线很好的替代品。文章分析了镀钯铜线作为键合线材料本身的基本性质,镀钯铜线引线键合的特征和镀钯铜线PCT实验的可靠性。通过分析发现镀钯铜线材料本身有优良的导电和导热特性,同时还有很好的抗氧化性。镀钯铜线在键合过程中需要保护气体的保护,通过硬度实验发现镀钯铜线的硬度较大,因此需要在键合过程中防止弹坑的出现。通过PCT实验证实镀钯铜线具有较好的可靠性。     

铜丝球焊工艺在low-k芯片材料上实现可靠焊接性能的研究

为降低成本和应对芯片工艺的发展,本文针对铜线在low-K芯片材料上应用所面临的挑战,进行了研究和分析,从原理和方法上对影响铜线键合的关键因素,如自由球,保护气,压力和超声进行了描述,阐明了为防止芯片出现裂纹或者弹坑的应对方法,以及提高铜线可靠性的遵循原则,使得铜线可以大量代替目前的金线焊接工艺,在基板集成电路芯片上获得...     

镀Pd Cu线键合工艺中Pd行为研究

由于Cu线热导率高、电性能好、成本低,将逐渐代替传统Au线应用于IC封装.但Cu线键合也存在Cu材料本身固有特性上的局限:易氧化、硬度高及应变强度等.表面镀Pd Cu线材料的应用则提供了一种防止Cu氧化的解决方案.然而,Cu线表面的Pd层很可能会参与到键合界面形成的行为中,带来新的问题,影响到Cu线键合的强度和可靠性.对镀Pd Cu线键合工艺中Pd的行为进行了系统的研究,使用了SEM,EDS等分析手段对cu线、烧结Cu球(FAB)、键合界面等处Pd的分布状况进行了检测,结果证明Pd的空间分布随着键合工艺的进行发生了很大的变化,同时还对产生Pd分布变化的原因进行了分析和讨论.     

毫米波射频互连微组装工艺优化研究

在毫米波产品的装配中,射频互连微组装工艺是影响产品性能的一个重要因素。采用三维电磁仿真软件对毫米波频段的组装缝隙宽度、金丝热超声楔焊跨距及拱高进行了建模仿真,分析了上述因素对驻波的影响。针对模拟仿真优化结果,给出了毫米波射频互连装配精度控制、接地焊接效果优化、金丝热超声楔焊线型及键合参数优化等相应的工艺优化措施,从而达到毫米波射频互连微组装工艺优化的目的。     

Modeling of copper wire bonding process on high power LEDs

In this paper, a couple thermal mechanical transient dynamic finite element framework of copper wire bonding process on high power lighting emitting diodes (LEDs) is developed, which considers the thermal heating effects of friction and plastic deformation. The whole wire bonding process is simplified to consist of impact and ultrasonic vibration stages. Parametric studies are also carried out to examine the effects of ultrasonic vibration amplitude and bonding force on stress/strain distribution and friction thermal heating effect during wire bonding process. Different friction coefficients of interface between the free air ball (FAB) and the bond pad are taken in the simulation to examine the effects of friction on the stress and strain level of electrode structure. Modeling results show that the stress/strain distribution and temperature evolution of wire bonding system are significant influenced by the ultrasonic vibration amplitudes, bonding forces and friction coefficients. Discussion and comparison are conducted between the copper and the gold wire bonding processes on the high power LEDs by numerical simulation. The results have disclosed that higher stress/strain in the bond pad and the ohmic contact layer is induced during the copper wire bonding process. Therefore, the process parameters of copper wire bonding should be controlled carefully. This numerical simulation work may provide guidelines for the copper wire bonding process virtual window development of high power LEDs packaging.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Comparison of the copper and gold wire bonding processes for LED packaging

Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame. The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of copper wire bonding process on the high power LED packaging.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

分立IGBT的封装技术研究

文章通过对单器件的分立IGBT的封装结构进行分析,针对其结构特点和封装技术要求,特别是封装关键工艺芯片切割的影响,对装片、焊接方面进行工艺研究。并通过试验分析解决实际生产所出现的技术问题,由此形成一套适应于大批量封装生产的IGBT封装工艺技术,成功地应用于分立IGBT器件的批量生产,保证了产品的可靠性,取得了很好的生产效益。     

Bonding parameters of blanket copper wafer bonding

A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications. In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature, duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding condition for 3-D integration can be determined.