完全自适应路由算法的虚通道分配优化策略

在虫孔交换的片上网络中,针对完全自适应路由算法对路由器缓存资源使用的不足,提出了一种虚通道分配优化策略.该策略通过比较输出虚通道的信用量计数与数据包剩余微片数的关系来确定处于缓存队列中的尾微片不会被阻塞在当前路由器中,从而将已被释放但尚未被排空的虚通道提前分配给正在等待的数据包,以提高对缓存资源的利用率.8×8mesh中的仿真结果表明,对比保守的虚通道分配方式,该优化策略能提高网络的饱和注入率,或者在保持网络性能相当的前提下减少对缓存资源的使用.     

用于片上光网络的光学路由器研究

基于SOI平台的硅基集成光学器件具有高带宽、低功耗、低延迟等优点,为实现片上光互连网络提供了一种可行的技术方案。光学路由器是片上光互连网络中负责节点数据交换的重要器件。介绍了国内外光学路由器的最新研究进展,并着重介绍了利用微环谐振器和马赫-曾德尔光开关构建N端口无阻塞光学路由器的一般性原理,进行了统计分析和仿真结果显示,应用一般性原理构建的光学路由器与之前已报道过的同规模光学路由器相比在开关个数、插入损耗、平均功耗等方面的性能均有所提升。     

三维片上网络故障及拥塞感知的容错路由器设计

 三维片上网络中路由器的输入端口和交叉开关出现故障,将严重影响整个网络的性能,因此文章提出了一种故障及拥塞感知的容错路由器.通过增加一个冗余的输入端口和旁路总线,不仅能实现对输入端口和交叉开关容错的目的,而且还能在没有端口故障的情况下使用冗余端口有效地解决拥塞问题.实验表明此容错机制能够使得网络在故障路由器多、拥塞严重的情况下,仍然保持良好的性能.     

交换结构中的可重构缓存机制

大量研究集中在路由器对缓存区容量设置的理论需求上,可重构缓存则借助可重构系统按需分配的思想,试图从实现机制上提高缓存利用率以改善系统性能。现有固定缓存的交换结构,在大量缓存区空闲时仍可能有某些端口因较大突发流量而大量分组丢失。为此引入缓存的重构机制,打破端口对缓存单元的私有独占,按各端口的实际缓存需求量来实时重构,分析和实验结果表明,运用该机制可有效解决缓存资源浪费现象,在获得同等抗突发性能的条件下,节约大量存储单元,大大提高路由器交换系统中存储单元的利用率。     

连接圭从IP核的片上网络路由器结构

随着单个芯片上集成的元器件数目不断增加,功耗问题也变得越来越突出。片上网络虽然能够从理论上解决传统总线结构带来的种种问题,但其功耗问题在某些具体应用中却变成了关键的制约因素。路由器作为片上网络的核心部件,其结构直接影响片上网络的性能。路由器的功耗问题已经成为片上网络领域一个热点问题。本文运用最优化理论对连接主从IP核的片上网络路由器结构进行优化设计,并运用路由器的功耗模型对功耗问题进行了分析。最后运用OPNET仿真软件对路由器的交换机制和路由算法进行分析对比,得出最终结论。     

一种适用于非对称主从IP核的低功耗路由器结构

大规模及超大规模集成电路的快速发展使片上网络系统成为现实,同时也使十几个平方厘米芯片的功耗达到了上百瓦,而且随着集成电路规模的发展,功耗参数也在不断上升。深微亚领域的研究使得片上网络芯片的面积不断缩小,从而使得IP核互连通信中时延和能耗成为了现代片上网络系统的主要考虑因素。本丈主要分析片上网络系统的平均时延以及内部负责主要通信任务的路由器的结构,功耗,及其功耗降低的方法。     

一种自适应低损耗三维有源光网络结构设计

针对三维有源光网络路径配置时间长、光路由器插入损耗大和网络硬件开销高等问题,文章设计了自适应路由算法和无阻塞、低损耗光路由器.自适应路由算法利用XYZ确定路由算法进行端口的初次判断,再根据端口阻塞情况进行二次判断,最终选择无阻塞和距离短的端口作为节点输出端口;针对三维通信需求分别设计层内6端口和层间3端口光路由器代替7...     

基于SRAM的核心路由器交换矩阵输入端口设计

交换矩阵是核心路由器的重要组成部分,为了避免来自不同输入端口的信元同时发往同一个输出端口,需要在输入端口设置缓冲区,即输入排队交换结构。基于静态随机存储器完成了交换矩阵输入端口虚拟输出队列（VOQ）的设计,该设计可以降低核心路由器交换芯片的面积,提高输入端口缓冲区信元的响应速率,并通过DE-115开发板完成对设计的验证。     

一种低延时片上网络路由器的设计与实现

通过分析流水线结构和单周期结构的片上网络路由器,提出了一种低延时片上网络路由器的设计,并在SMIC0.13um Mixed-signal/RF 1.2V/3.3V工艺进行流片验证。芯片测试结果表明,该路由器可以在300 MHz时钟频率下工作,并且在相同负载下,与其他结构的路由器相比较,其能够在较低延时下完成数据包传送功能。     

面向片上光互连的无源H树网络设计

传统的片上电互连已无法满足多核处理系统日益 增长的通信需求,在延迟、能耗和 带宽方面更具优势的片上光互连逐渐引起关注。为了降低片上光网络(optical network-on-chip,ONoC)硬件开销和提升光网络 性能,本文提出一种基于微环谐振器的16端口无源H树光互连网络。利用宽带微环谐振器设 计4组转向光路由器,降低微环谐振器使用并完成端口选择,将信号传输到8端口接收光路由 器以及3级和4级光开关来满足信号的无争用传输。实验结果表明,在16×16阵列规模下与 Crossbar、λ-Router、GWOR、LACE、Light等无源网络结 构相比,无源光H树网络仅需使用 72个微环谐振器。网络平均插入损耗1.49 dB,与λ-Router、GWOR 、TAONoC相比分别降低 了21.5%、10.7%、59.7 %,各路径平均信噪比 为17.48 dB,与λ-Router、GWOR、Light相比分别提高了38.5%、36.0%、17.1%。     

QBNoC: QoS-aware bufferless NoC architecture

Chip area and power consumption are the main restrictions for Network-on-Chip (NoC), a high proportion of which is consumed by the buffers in the routers. Therefore, bufferless NoC, which completely eliminates in-router buffers, has been proposed. However, the existing bufferless NoC designs do not provide Quality-of-Service (QoS) guarantee. In this paper, we propose a QoS-aware Bufferless NoC, named QBNoC. QBNoC employs hybrid switching mechanism, namely circuit switching mechanism for real-time application and wormhole switching mechanism for other applications. Besides, in order to decrease the deflection probability and thus improve the performance of the network, we propose a new output port allocation policy, named Two-Stage Allocation (TSA). Furthermore, new router architecture with shorter critical path is designed for QBNoC. The evaluation results show that by efficiently exploiting resources, our proposal significantly improves the performance of the whole network, and meanwhile satisfies the QoS requirements of different applications.     

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures.     

A load balancing bufferless deflection router for network-on-chip

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip (NoC) design. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router (LBBDR) for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.     

Network-on-Chip design and synthesis outlook

With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication requirements of MPSoCs made of hundreds of cores will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products.

To overcome these problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. However, the development of application-specific NoCs for MPSoCs is a complex engineering process that involves the definition of suitable protocols and topologies of switches, and which demands adequate design flows to minimize design time and effort. In fact, the development of suitable high-level design and synthesis tools for NoC-based interconnects is a key element to benefit from NoC-based interconnect design in nanometer-scale CMOS technologies.

In this article we overview the benefits of state-of-the-art NoCs using a complete NoC synthesis flow, and a detailed scalability analysis of different NoC implementations for the latest nanometer-scale technology nodes. We present NoC-based solutions for the on-chip interconnects of MPSoCs that illustrate the benefits of competitive application-specific NoCs with respect to more regular NoC topologies regarding performance, area and power. Moreover, we show that it is currently feasible to synthesize in an automatic way a complete custom NoC interconnect from a high-level specification in few hours. Finally, we summarize future research challenges in the area of NoC interconnect design automation.     

High-level customization framework for application-specific NoC architectures

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.     

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

A hardened network-on-chip design using runtime hardware Trojan mitigation methods

Due to the globalized semiconductor business model, malicious hardware modifications, known as hardware Trojans (HTs), have risen up as a big concern for chip security. HT detection and mitigation methods for general integrated circuits have been investigated in the past decade. However, the majority of the existing efforts are not customized for HTs in Networks-on-Chip (NoCs). To complement the firmware and software level methods for rogue NoCs detection, we propose countermeasures to harden the NoC hardware design against tampering. More specifically, we propose a collaborative dynamic permutation and flit integrity check method to mitigate the potential inside-router HTs inserted by the disloyal member in the NoC design house or the 3^rd-party system integration company. Our method improves the number of received packets by up to 70.1% over the other methods if the HT controls the NoC packet destination address. The average link availability of our method is 43.7% higher than that of the exiting methods. Our method increases the effective average latency by up to 63.4%, 68.2%, and 98.9% for the single HT in the destination, header, and tail fields, respectively, over the existing methods.     

Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services

Best Effort (BE) and Guaranteed Throughput services (GT) are the two broad categories of communication services provided in NoC. Few of the existing NoC architectures provide both of these services. GT based services, which are based on circuit switching or connection oriented mechanisms of packet switching, are usually preferred for real time traffic while packet switching services are provided by the BE architecture. In this paper, biologically inspired fault tolerant techniques are implemented on these two different services. Biologically inspired techniques offer novel ways of making NoCs fault tolerant; faults in NoCs arise partly due to advanced nanoscale manufacturing processes and the complex communication requirements of the processing elements (PEs). The proposed NoCs fault-tolerant methods (synaptogenesis and sprouting) are adapted from the biological brain׳s robust fault tolerant mechanisms. These techniques are implemented on both BE and GT services. From the experimental results, the BE architecture was efficiently utilizing the bandwidth compared to GT services, while throughput utilization of GT services were better. The accepted traffic (flit/cycle/node) of the BE architecture is 6.31% better than GT architecture while the accepted traffic of the bio-inspired techniques is 72.12% better than traditional fault tolerant techniques.     

A low-overhead and reliable switch architecture for Network-on-Chips

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation of the erroneous flits in NoC is prevented without any need to credit signals and, retransmission buffers. Using an HDL-based NoC simulator, the LRS is compared to two other widely used reliability enhancement methods: the Switch-to-Switch (S2S) and the End-to-End (E2E) methods. The simulation results show that the LRS consumes less power and provides higher performance compared to those of the E2E and S2S methods. More importantly, unlike the E2E and the S2S methods, the LRS has constant overheads, which makes it applicable in all working conditions. To validate the comparison, an analytical performance and reliability model is developed for the LRS, S2S and E2E methods. The results of the model match those obtained from the simulations while the proposed model is significantly faster.     

Selective congestion control for mixed-critical networks-on-chip

Modern Networks-on-Chip (NoCs) must accommodate a diversity of temporal requirements, e.g., providing guarantees for real-time senders while reducing adverse performance impact on best-effort (BE) traffic. In this work, we propose a protocol-based adaptive congestion control. By selectively detouring real-time or BE traffic (i.e load balancing) and dynamic throttling of BE, we allow improving the NoC performance without costly hardware extensions. The introduced method offers safe and efficient integration of mixed-critical workloads through the coupling of flow control mechanisms with the path selection based on the current NoC state. The requested real-time reliability of the network is achieved through a predictable synchronization with control messages supported by a formal analysis and an experimental evaluation.