Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed.     

Plasma reflow bumping of Sn-3.5 Ag solder for flux-free flip chip package application

A new flux-free reflow process using Ar+10%H/sub 2/ plasma was investigated for application to solder bump flip chip packaging. The 100-/spl mu/m diameter Sn-3.5wt%Ag solder balls were bonded to 250-/spl mu/m pitch Cu/Ni under bump metallurgy (UBM) pattern by laser solder ball bonding method. Then, the Sn-Ag solder balls were reflowed in Ar+H/sub 2/ plasma. Without flux, the wetting between solder and UBM occurred in Ar+H/sub 2/ plasma. During plasma reflow, the solder bump reshaped and the crater on the top of bump disappeared. The bump shear strength increased as the Ni/sub 3/Sn/sub 4/ intermetallic compounds formed in the initial reflow stage but began to decrease as coarse (Cu,Ni)/sub 6/Sn/sub 5/ grew at the solder/UBM interface. As the plasma reflow time increased, the fracture mode changed from ductile fracture within the solder to brittle fracture at the solder/UBM interface. The off-centered bumps self-aligned to patterned UBM pad during plasma reflow. The micro-solder ball defects occurred at high power prolonged plasma reflow.     

倒装芯片组装集成电路开封方法

倒装芯片组装集成电路的结构与常规封装不同,导致现行开封技术不完全适用于倒装芯片组装集成电路。对不同封装形式的倒装芯片组装集成电路结构分析,找出目前制约开封技术的关键因素。以陶瓷及塑封封装倒装芯片组装集成电路为例,运用热风枪、高温预处理、机械应力及化学腐蚀等方法,提出了一套适用性强、效率高的综合性倒装芯片组装集成电路开封工艺技术,并通过实例进行验证和总结。通过运用该技术可以有效解决倒装芯片组装集成电路的开封问题,为后续标准的修订及破坏性物理分析提供依据和帮助。     

Solder wetting in a wafer-level flip chip assembly

Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated     

Development of gold based solder candidates for flip chip assembly

Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders for interconnecting the chip to a carrier in certain applications due to the unique properties of lead. Despite of all the beneficial attributes of lead, its potential environmental impact when the products are discarded to land fills has resulted in various legislatives to eliminate lead from the electronic products based on its notorious legacy as a major health hazard across the spectrum of human generations and cultures. Flip chip assembly is also now increasingly being used for the high-performance (H-P) systems. These H-P systems perform mission-critical operations and are expected to experience virtually no downtime due to system failures. Thus, reliability of the solder joint is a major critical issue. This reliability is directly influenced by both the phases in the bulk solder and also the intermetallic compounds formed between the solder and the solder wettable layer of the under-bump metallization during both the wetting reaction or/and the solid state ageing. In the present work, an attempt has been made to develop new solder alloys for flip chip assembly using the CALPHAD approach based on gold, the safest element among all the elements being considered for this application. Specifically, efforts have been made to predict the phases in the bulk solder of the promising solder candidates and also the intermetallic compounds formation, using the CALPHAD approach.     

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

Electroplating is the best process for the manufacture of fine pitch flip chip solder bumps. However, certain unstable electroplating parameters usually cause poorer coplanarity, which affects packaging reliability and yield. This paper attempts to utilize a CMP-like polisher to reduce the nonuniform height deviation after electroplating. The optimization of three major polishing parameters—pad hardness, loading pressure, and polishing speed—enables the polisher to have a higher material removal rate (MRR) and an easier manipulation as compared with chemical mechanical polishing (CMP). After polishing at a pitch size of 100 μm, the overall coplanarity could be decreased sharply from 33±2.5 μm (coplanarity=7.5%) to 28±1 μm (coplanarity=3%) and it even reached 26±0.5 μm (coplanarity=1%) after reflow.     

Test structure assembly for bump bond yield measurement on high density flip chip technologies

Modern flip chip technologies for imaging applications have achieved a very high integration level together with the possibility of large area assemblies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly. Consequently, yield tests become difficult, and an accurate measurement of it is often discarded. This problem is aggravated in medical applications, where the critical information can be limited to a few pixels, and therefore, yield should be very close to 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between an usable and a non-usable assembly. Therefore, quantitative and precise measurement of bump bond yield is needed to characterize the quality of any high density flip chip technology for these applications. In this paper, we present a newly developed test structure for electrical measurement of the bump bond yield of high density flip chip technologies, allowing both optimization and statistical control of the process. This test structure facilitates the identification of possible process deviations with precise quantitative yield measurements. It also allows to pin point any localized systematic failure in the bump bonding process. The test structure has been used to evaluate the yield of different flip chip technologies and has contributed to their fine optimization where necessary.     

倒装芯片凸焊点的UBM

介绍了倒装芯片凸焊点的焊点下金属（UBM）系统,讨论了电镀Au凸焊点用UBM的溅射工艺和相应靶材、溅射气氛的选择,给出了凸焊点UBM质量的考核试验方法和相关指标。     

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

A new defect in which a chip "floats" over the board surface after chip placement is appearing in the low-cost, high-throughput flip chip on board (FCOB) assembly that is based on no-flow underfill. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." A process model has been developed that will allow an understanding of the underlying physics of the floating phenomena and identification of process variables so that this process defect can be eliminated. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the theoretical model's predictions.     

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly

In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the I_ON current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. Additionally, the package out of plane deformation has been measured after flip chip to laminate and after molding. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress. It has also been shown that the out of plane deformation is independent of the Cu pillar design.     

Coaxial transitions for CPW-to-CPW flip chip interconnects

A novel coaxial transition for CPW-to-CPW flip chip interconnect is presented and experimentally demonstrated. To realise the coaxial transition on the CPW circuit, benzocyclobutene was used as the interlayer dielectric between the vertical coaxial transition and the CPW circuit. The coaxial interconnect structure was successfully fabricated and RF characterised to 67 GHz. The structure showed excellent interconnect performance from DC up to 55 GHz with low return loss below 20 dB and low insertion loss less than 0.5 dB even when the underfill was applied to the structure.     

Parametric compact models for flip chip assemblies

A parametric thermal compact modeling study of flip chip assemblies is presented. First, a star network of four thermal resistors was found to be optimal for a flip chip with arbitrary geometry and material properties. In a second step several parameters such as thermal underfill conductivity and die size were varied. The effect of these variations on the values of the four thermal resistors of the compact model is investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility of choosing a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model. Having the compact model, it is now possible to apply customer specific boundary conditions to this compact model and compute the maximal temperature reached at the junction of the flip chip assembly in the specified environment     

Cycling copper flip chip interconnects

Use of flip chip assembly on compound semiconductor circuits is relatively new. Although solder bumping has been around for a while, use of copper bumps is also new. This discussion is intended to provide some initial data on the melding of copper flip chip bumps and compound semiconductor technologies, with respect to thermal excursion testing––cycling. For comparison, it is known that attempts to accelerate degradation caused by thermal excursions on solder bumps can result in irregular failure mechanisms. This work shows that on-chip power cycling can be used to cause identical failure mechanisms to those caused by normal temperature cycling.     

Redistribution and bumping of a high I/O device for flip chipassembly

Redistribution and bumping of a high I/O device has been successfully achieved at Motorola's Interconnect Prototype Lab using a combination of photosensitive benzocyclobutene (BCB), electroless nickel underbump metallurgy, and photoresist defined solder printing technique. To take full advantage of flip chip packaging technology, redistribution is necessary to rewire bondpads to an area array. BCB was chosen as the interlayer dielectric between the redistributed metal traces and device circuitry. Advantages of BCB include high level of planarization, low moisture uptake, rapid thermal curing, high thermal stability, high solvent resistance, and a low dielectric constant. We successfully optimized many steps in the process flow to redistribute the bondpads. The BCB residue in vias was cleaned with a plasma descum comprised of an Ar/SF₆ mixture. BCB to BCB adhesion was improved by optimizing the curing time. The shear strength of the bumps was increased 80% by sputter-roughening of the BCB/Al interface. Sematech ATC04-2 functional wafers with 1004 bumps/die and a minimum pitch of 8 mils were successfully redistributed to a 10 mil and 16 mil mixed array pitch and solder bumped using a photodefined squeegee bump technology     

Reduced thermal strain in flip chip assembly on organic substrateusing low CTE anisotropic conductive film

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances, resulting in a high performance and cost-competitive packaging method. This paper describes the usefulness of low cost flip-chip assembly using electroless Ni/Au bump and anisotropic conductive films on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed as a low cost bumping method. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with Ni₃P precipitation above 300°C causes an increase of hardness and an increase of the intrinsic stress. As interconnection material, modified ACFs composed of nickel conductive fillers for conductive fillers, and nonconductive fillers for modification of film properties, such as coefficient of thermal expansion (CTE), were formulated for improved electrical and mechanical properties of ACF interconnection. Three ACF materials with different CTE values were prepared and bonded between Si chips and FR-4 boards for the thermal strain measurement using moire interferometry. The thermal strain of the ACF interconnection layer, induced by temperature excursion of 80°C, was decreased according to the decreasing CTEs of ACF materials. This result indicates that the thermal fatigue life of ACF flip chip assembly on organic boards, limited by the thermal expansion mismatch between the chip and the board, could be increased by low CTE ACF     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.