Application of Al/PI composite bumps to COG bonding process

This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm² and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process     

Multiple-chip precise self-aligned assembly for hybrid integratedoptical modules using Au-Sn solder bumps

We have developed a novel three-dimensional high precision self-aligned assembly using stripe-type Au-Sn solder bumps and a micro-press solder bump formation method. This produces a high bonding precision of 1 μm for optical device assembly in both lateral and vertical directions without the need for time-consuming optical axes alignment. Furthermore, we tested a hybrid integrated 4×4 optical matrix switch, in which multiple SSC-SOAG arrays were simultaneously positioned and optical fibers were passively positioned on a silica based PLC platform using this technology. Four optical chips and seven wiring chips are assembled on a planar lightwave circuit (PLC) platform. The insertion loss for each of these paths at an injection current of 40 mA was within a range of 9±4 dB. The average extinction ratio was 40 dB. This self-aligned assembly technology was shown to be useful for building hybrid-integrated multichannel optical network components     

Characterization of flip chip bonded structure with Cu ABL power bumps

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E−8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated.     

Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件—智能像素面阵 ,对倒装焊的工艺过程作了简要的介绍。该面阵采用铟做凸点材料 ,制作了输入输出数达 6 4× 6 4的凸点电极阵列 ,并采用回流焊的方式 ,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接 ,形成输入输出引线间距只有 80 μm的面阵器件     

Thermosonic flip-chip bonding for SAW filter

A flip-chip bonding (FCB) method suitable for the surface acoustic wave (SAW) filter was developed. In this method, the gold-ball bumps formed on the chip are directly bonded onto the ceramic substrate by thermosonic bonding. After FCB, they are sealed with a cap without using underfill resin. To obtain high bond strength, characteristic properties of the substrate electrode and the ball bump, were optimized. Furthermore, bondability has been improved by adopting a ramp-up loading profile. The reliability test was carried out with 6-pin SAW chips, and we confirmed the sufficient reliability of bonds.     

Flip-chip planar GaInAs/InP p-i-n photodiodes-fabrication andcharacteristics

New flip-chip planar GaInAs/InP p-i-n photodiodes have been fabricated as an array. We describe the structure of the photodiode, the design of a microlens, the fabrication processes, characteristics, and the optical fiber-coupled modules. This photodiode satisfied the requirements for a small junction capacitance and low dark current, good optical fiber coupling, and easy fabrication. We obtained a low dark current with good reproducibility by using two layer polyimide and SiN passivation films. A microlens with a 50 μm φ to 120 μm φ aperture could easily be fabricated with an InP-substrate. By electroplating, flip-chip metal bumps were directly formed on the active region of the photodiode for the first time     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

A new flip-chip bonding technique using micromachined conductivepolymer bumps

Using micromachining techniques with thick photoresists, a new conductive polymer flip-chip bonding technique that achieves both a low processing temperature and a high bumping alignment resolution has been developed in this work. By the use of UV-based photolithography with thick photoresists, molds for the flip-chip bumps have been patterned, filled with conductive polymers, and then removed, leaving molded conductive polymer bumps. After flip-chip bonding with the bumps, the contact resistances measured for 25 μm-high bumps with 300 μm×300 μm area and 400 μm×400 μm area were 35 mΩ and 12 mΩ respectively. The conductive polymer flip-chip bonding technique developed in this work shows a very low contact resistance, simple processing steps, a high bumping alignment resolution (<±5 μm), and a lower bonding temperature (~170°C). This new bonding technique has high potential to replace conventional flip-chip bonding technique for sensor and actuator systems, bio/chemical μ-TAS, optical MEMS, OE-MCM's, and electronic system applications     

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 ± 3.5 μm, and a maximum-to-minimum bump height range of 17 μm over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 μm peripheral pitch. A 109.6 ± 1.3 μm bump height on orthogonal array with 250 μm pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 × reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +125°C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121°C, 100% RH, 15 psig test condition     

Increasing bondability and bonding strength of gold stud bumps onto copper pads with a deposited titanium barrier layer

A flip-chip assembly is an attractive scheme for use in high performance and miniaturized microelectronics packaging. Wafer bumping is essential before chips can be flip-bonded to a substrate. Wafer bumping can be used for mechanical-single point stud bump bonding (SBB), and is based on conventional thermosonic wire bonding. This work proposes depositing a titanium barrier layer between the copper film and the silver bonding layer to achieve perfect bondability and sufficiently strong thermosonic bonding between a stud bump and the copper pad.A titanium layer was deposited on the copper pads to prevent copper atoms from out-diffusing during thermosonic stud bump bonding. A silver film was then deposited on the surface of the titanium film as a bonding layer to increase the bondability and bonding strength for stud bumps onto copper pads. The integration of the silver bonding layer with a diffusion barrier layer of titanium on the copper pads yielded 100% bondability between the stud bump and pads. The strength of bonding between the gold bumps on the copper pads significantly exceeds the minimum average values in JEDEC specifications. The diffusion barrier layer of titanium effectively prevents copper atoms from out-diffusing to the silver bonding layer surface during thermosonic bonding, which fact can be interpreted with reference to the experimental results of energy dispersive spectrometry (EDS) and analyses of Auger depth profiles. This diffusion barrier layer of titanium efficiently provides perfect bondability and sufficiently strong bonding between a stud bump and copper pads with a silver bonding layer.     

Optimal design toward enhancement of thermomechanical reliability of polyimide layers in a flip-chip-on-lead-frame dual flat no-leads package with copper pillar bumps

Thermomechanical reliability of polyimide layers in a flip-chip-on-lead-frame dual flat no-leads package subjected to thermal cycling test condition was studied by the finite element method and the Taguchi method. Different control factors were considered for optimal design toward enhancement of the thermomechanical reliability of polyimide layers, including diameter of the Cu pillar bumps, polyimide opening, and size of the Al pad. Conforming to design rules, the largest Al pad diameter, the smallest size of bump diameter, and the largest polyimide opening were found to be beneficial to enhance the thermomechanical reliability of polyimide layers. And the optimal design was experimentally verified.     

HTS and PCT Reliability of Chips and Flex Substrates Assembled Using a Thermosonic Flip-Chip Bonding Process

This study assesses the high-temperature storage (HTS) test and the pressure-cooker test (PCT) reliability of an assembly of chips and flexible substrates. After the chips were bonded onto the flexible substrates, specimens were utilized to assess the HTS test and PCT reliability. After the PCT and HTS tests, the die-shear test was applied to examine changes in die-shear forces. The microstructure of the test specimens was analyzed to evaluate reliability and to identify possible failure mechanisms. When the duration of the HTS test was increased, the percentage of gold bumps that peeled off from the surface of the copper pads on the chip side increased, and a crack was present at the bonding interface between the gold bumps and chip bond pads. This crack was due to thermal stress generated during the HTS test, and degraded the die-shear force of the assembly of chips and flexible substrates. After the PCT, the crack was present at the interface between deposited layers of copper electrodes after the specimens were subjected to the PCT for various durations. Moisture penetrated into the deposited layers of the copper electrodes, deposited layers lost their adhesion, and the crack progressed from the corner into the central bond area as the test duration increased. To improve the PCT reliability of assemblies of chips and flexible substrates using the thermosonic flip-chip bonding process, one must prevent moisture from penetrating into deposited layers of copper electrodes and prevent crack formation at the interface between nickel and copper layers. Underfill would be an effective approach to prevent moisture from penetrating into deposited layers during the PCT, thereby improving the reliability of the samples during the PCT.     

High-throughput mapping of short-range spatial variations usingactive electrical metrology

Spatial variations of parameters in semiconductor manufacturing, such as critical dimension (CD) and overlay, have significant impact on the performance and yield of integrated circuits (IC). Among these spatial variations, the variations of parameters between transistors separated by a very short spatial distance such as 1 μm to 100 μm (intertransistor variations) can be particularly hazardous for those types of ICs that require exact transistor-transistor matching. To measure these intertransistor variations, both high-throughput and high-spatial-sampling-density beyond the scope of currently available metrology tools are needed. We have thus developed an active electrical metrology method of measuring intertransistor variations using on-chip, active, electrically addressable arrays of test structures to provide the high-throughput (5 μs/data point) and high-density (3 μm/grid spacing) needed. Test chips were designed and fabricated on a HP 0.35-μm process, and the testing configuration was set up to optimize throughput and precision. This method was verified with the measurements of on-chip calibration arrays. The spatial variations of both intertransistor CD (effective gate length) and overlay (between poly/diffusion) within the test chips were mapped with this method. For these circuits, the intertransistor CD variations were found to depend primarily on the layout, whereas the intertransistor overlay variations were found to be dominated by errors of the pattern generator used to fabricate the masks     

Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection

In this paper, we describe hybrid bonding technology of single-micron pitch with planar structure for three-dimensional (3D) interconnection. Conventionally, underfill method utilizing capillary force was used after the bonding of microbump. However, the filling becomes insufficient in a gap less than 10 μm between chips or bumps. One promising technology is the hybrid bonding technology that microbumps and an adhesive can be simultaneously bonded. To realize a single-micron pitch hybrid bonding, we fabricated a planar structure that consists of 8 μm-pitch Cu/Sn microbumps and a non-conductive film (NCF) by a chemical mechanical polishing (CMP) of resin. After planarization, the Cu/Sn bumps and the NCF were simultaneously bonded at 250 °C for 60 s. Cross-sectional scanning electron microscope (SEM) images and energy dispersive X-ray spectroscopy (EDX) images show that the adhesive resin on the bump surface was successfully removed by the CMP. In addition, SEM images of the bonded sample show that the adhesive filled the 2.5-μm gap between the chip and substrate. The Cu/Sn bumps were properly bonded in a corner on the chip. The proposed bonding method is expected to enable single-micron pitch interconnection for ultra-high density 3D LSI of next generation.     

Experimental characterization and mechanical behavior analysis of intermetallic compounds of Sn–3.5Ag lead-free solder bump with Ti/Cu/Ni UBM on copper chip

Due to today’s trend towards ‘green’ products, the environmentally conscious manufacturers are moving toward lead-free schemes for electronic devices and components. Nowadays the bumping process has become a branch of the infrastructure of flip chip bonding technology. However, the formation of excessively brittle intermetallic compound (IMC) between under bump metallurgy (UBM)/solder bump interface influences the strength of solder bumps within flip chips, and may create a package reliability issue. Based on the above reason, this study investigated the mechanical behavior of lead-free solder bumps affected by the solder/UBM IMC formation in the duration of isothermal aging. To attain the objective, the test vehicles of Sn–Ag (lead-free) and Sn–Pb solder bump systems designed in different solder volumes as well as UBM diameters were used to experimentally characterize their mechanical behavior. It is worth to mention that, to study the IMC growth mechanism and the mechanical behavior of a electroplated solder bump on a Ti/Cu/Ni UBM layer fabricated on a copper chip, the test vehicles are composed of, from bottom to top, a copper metal pad on silicon substrate, a Ti/Cu/Ni UBM layer and electroplated solder bumps. By way of metallurgical microscope and scanning-electron-microscope (SEM) observation, the interfacial microstructure of test vehicles was measured and analyzed. In addition, a bump shear test was utilized to determine the strength of solder bumps. Different shear displacement rates were selected to study the time-dependent failure mechanism of the solder bumps. The results indicated that after isothermal aging treatment at 150 °C for over 1000 h, the Sn–Ag solder revealed a better maintenance of bump strength than that of the Sn–Pb solder, and the Sn–Pb solder showed a higher IMC growth rate than that of Sn–Ag solder. In addition, it was concluded that the test vehicles of copper chip with the selected Ti/Cu/Ni UBMs showed good bump strength in both the Sn–Ag and Sn–Pb systems as the IMC grows. Furthermore, the study of shear displacement rate effect on the solder bump strength indicates that the analysis of bump strength versus thermal aging time should be identified as a qualitative analysis for solder bump strength determination rather than a quantitative one. In terms of the solder bump volume and the UBM size effects, neither the Sn–Ag nor the Sn–Pb solders showed any significant effect on the IMC growth rate.     

Golden bump for 20 micron diameter wire bond enhancement at reduced process temperature

With the rapid development of advanced microelectronic packaging technologies, research on fine-pitch wire bonding with improved reliability is driven by demands for smaller form factors and higher performance. In this study, thermosonic wire bonding process with a 20 μm wire for fine-pitch interconnection is described. To strengthen stitch bonds made in a gold-silver bonding system when the bonding temperature is as low as 150 °C, ball bumps (security bump) are placed on top of the stitch bonds. The ball-stitch bond and bump forming parameters are optimized using a design of experiment (DOE) method. A comparison of pull test results for stitch bonds with and without security bumps shows a substantial increase of the stitch pull force (PF) due to the use of security bonds. By varying the relative position of the security bumps to the stitch bonds via wedge shift offset (WSO), a WSO window ranging from 15 to 27 μm results in stitch PF higher than 7 gf, which is equivalent to an increase in average stitch PF of 118%.