Fluorine Passivation in Gate Stacks of Poly-Si/TaN/HfO2 (and HfSiON/HfO2)/Si Through Gate Ion Implantation

Fluorine passivation in poly-Si/TaN/HfO₂/p-Si and poly-Si/TaN/HfSiON/HfO₂/p-Si gate stacks with varying TaN thickness through gate ion implantation has been studied. It has been found that when TaN thickness was less than 15 nm, mobility and subthreshold swing improved significantly in HfO₂ nMOSFETs; while there was little performance improvement in HfSiON/HfO₂ nMOSFETs due to the blocking of F atoms by the HfSiON layer in gate dielectrics, as has been proved by the electron energy loss spectroscopy mapping     

Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

高k HfLaO栅介质MoS2晶体管的性能研究

比较研究了HfO₂与HfLaO栅介质多层MoS₂场效应晶体管。实验结果表明,与HfO₂栅介质MoS₂晶体管相比,HfLaO栅介质MoS₂晶体管表现出更优的电性能。电流开关比高达1×10⁸,亚阈斜率低至76 mV/dec,界面态密度低至1.1×10¹² cm-2·eV-1,载流子场效应迁移率高达1×10⁹ cm²·V-1·s-1。性能改善的原因在于镧(La)对HfO₂的掺杂形成HfLaO化合物,减小栅介质薄膜的表面粗糙度,降低缺陷电荷密度,改善了栅介质/沟道界面特性,从而减小了界面态密度,抑制了库仑散射和界面粗糙散射。最终,提高了多层MoS₂晶体管的场效应迁移率,改善了晶体管的亚阈特性。     

Charge Trapping and TDDB Characteristics of Ultrathin MOCVD HfO2 Gate Dielectric on Nitrided Germanium

In this letter, we investigate the long-term reliability characteristics of ultrathin HfO₂ dielectrics on nitrided germanium for the first time. Stress-polarity dependence in charge trapping and time-dependent dielectric-breakdown (TDDB) characteristics has been observed in germanium nand p-type devices. The p-MOS devices exhibit severe charge trapping under stress, while no significant charge trapping and stress-induced leakage current were found in the n-MOS devices. In terms of operation-voltage projection for a ten-year lifetime, V_g=2.8 and -2.1 V is projected for the germanium p- and n-MOS devices, respectively, with an equivalent oxide thickness of 11 Aring. Compared to Si control samples, germanium devices show a comparable projected operation voltage, indicating that the TDDB for high-kappa dielectrics on nitrided germanium is not a concern. The stress-polarity dependence in germanium devices is believed to result from the asymmetrical band structure and the significant difference of the electric field strength across the gate dielectric between the positive and negative stress conditions     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made     

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ HfO2 Gate Stack

The low-frequency noise of pMOSFETs fabricated in epitaxial germanium-on-silicon substrates is studied. The gate stack consists of a TiN/TaN metal gate on top of a 1.3-nm equivalent oxide thickness HfO₂/SiO₂ gate dielectric bilayer. The latter is grown by chemical oxidation of a thin epitaxial silicon film deposited to passivate the germanium surface. It is shown that the spectrum is of the 1/f^gamma type, which obeys number fluctuations for intermediate gate voltage overdrives. A correlation between the low-field mobility and the oxide trap density derived from the 1/f noise magnitude and the interface trap density obtained from charge pumping is reported and explained by considering remote Coulomb scattering     

Influence of passivating interlayer on Ge/HfO2 and Ge/Al2O3 interface band diagrams

The energy band alignment between Ge, HfO₂ and Al₂O₃ was analyzed as influenced by passivating interlayers (ILs) of different composition (GeO₂, Ge₃N₄, Si/SiO_x). From internal photoemission and photoconductivity experiments we found no IL-sensitive dipoles at the Ge/HfO₂ interfaces, the latter being universally characterized by conduction and valence band offsets of 2.1 and 3.0 eV, respectively. However, in the case of HfO₂ growth using H₂O-based atomic layer deposition, the Ge oxide IL appears to have a narrower bandgap, 4.3 eV, than the 5.4–5.9 eV gap of bulk germania. Accordingly, formation of this IL yields significantly reduced barriers for hole and, particularly, electron injection from Ge into the insulator. Changing to a H-free process for HfO₂ and Al₂O₃ deposition suppresses the formation of the narrow-gap Ge oxide.     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

表面钝化对HfTiON栅介质Ge MOS电容性能的影响

通过NO、N2O对Ge衬底进行表面钝化,生长GeOxNy界面层,然后采用反应磁控共溅射方法制备HfTiN薄膜,并利用湿N2气氛退火,将HfTiN转化为HfTiON高κ栅介质.研究了表面钝化对MOS器件性能的影响,结果表明,湿NO表面钝化能改善界面质量,有效降低MOS电容的栅极漏电流,增强器件的可靠性.     

Ferroelectricity-modulated resistive switching in Pt/Si:HfO2/HfO2-x/Pt memory

It is investigated for the effect of a ferroelectric Si:HfO₂ thin film on the resistive switching in a stacked Pt/Si:HfO₂/highly-oxygen-deficient HfO_2-x/Pt structure. Improved resistance performance was observed. It was concluded that the observed resistive switching behavior was related to the modulation of the width and height of a depletion barrier in the HfO_2-x layer, which was caused by the Si:HfO₂ ferroelectric polarization field effect. Reliable switching reproducibility and long data retention were observed in these memory cells, suggesting their great potential in non-volatile memories applications with full compatibility and simplicity.     

铪/二氧化铪基双极阻变存储器特性研究

本文制备了纳米级Hf/HfO2阻变存储器（RRAM）。RRAM顶层电极和底部电极交叉,从而形成了金属-氧化物-金属结构。系统地研究了RRAM的电学特性,包括forming过程,SET过程和RESET过程。讨论了SET电压和RESET电压的相关性,以及高阻态和低阻态的相关性。RRAM的电学特性与SET过程中的限制电路强相关。可以基于量子点接触模型,阐述纳米级Hf/HfO2阻变存储器的导通机制。     

Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm² middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface     

LaON钝化层改善HfTiO高k栅介质Ge MOS电容电特性（英文）

采用溅射法淀积一层LaON薄膜作为钝化层,制备了HfTiO栅介质Ge MOS电容,并对它们的电特性进行了仔细研究。HfTiO/LaON堆栈栅介质Ge MOS电容呈现出许多比HfTiO Ge MOS电容更好的电特性,如更低的界面态密度(4.5×10~(11)eV~(-1)/cm~2)、更小的栅极漏电流(1.08×10~(-5)A/cm~2 at V_(fb)+1 V)和更大的k值(24.8)。获得这些结果的机理在于LaON钝化层能有效阻止O、Ti、Hf和Ge的相互扩散,从而抑制HfGeTiO界面层的生长。HfTiO/LaON是高质量Ge MOS器件有前途的高k栅介质。     

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Electrical characterisation and reliability of HfO2 and Al2O3–HfO2 MIM capacitors

Current leakage and breakdown of MIM capacitors using HfO₂ and Al₂O₃–HfO₂ stacked layers were studied. Conduction in devices based upon HfO₂ layers thinner than 8 nm is probably dominated by tunnelling. Al₂O₃–HfO₂ stacked layers provide a limited benefit only in term of breakdown field. Constant-voltage wear-out of samples using insulating layer thicker than 6 nm is dominated by a very fast increase of the leakage current. A two step mechanism involving the generation of a conduction path followed by a destructive thermal effect is proposed to explain breakdown mechanism.     

Characterization of the annealing impact on La2O3/HfO2 and HfO2/La2O3 stacks for MOS applications

The impact of various rapid thermal annealing used during the integration on the La₂O₃/HfO₂ and HfO₂/La₂O₃ stacks deposited by Atomic Layer deposition was analyzed. The consequences of lanthanum localization in such stacks on the evolution of the films during the rapid thermal annealing are investigated in term of morphology, crystalline structure, silicate formation and film homogeneity as a function of the depth. It appeared that the La₂O₃ location has an impact on the temperature of the quadratic phase formation which could be linked to the formation of SiOHfLa silicate and the resistance of the films to dissolution in HF 0.05 wt%.     

Fabrication and Performance of 0.25-$mu$m Gate Length Depletion-Mode GaAs-Channel MOSFETs With Self-Aligned InAlP Native Oxide Gate Dielectric

The fabrication and performance of 0.25- mum gate length GaAs-channel MOSFETs using the wet thermal native oxide of InAlP as the gate dielectric are reported. A fabrication process that self-aligns the gate oxidation to the gate recess and metallization to reduce the source access resistance is demonstrated for the first time. The fabricated devices exhibit a peak extrinsic transconductance of 144 mS/mm, an on-resistance of 3.46 Omega-mm, and a threshold voltage of -1.8 V for typical 0.25 -mum gate devices. A record cutoff frequency of 31 GHz for a GaAs-channel MOSFET and a maximum frequency of oscillation f_max of 47 GHz have also been measured.     

Electron states at the (1 0 0)Ge/HfO2 Interface

The energy distribution of extended and localized electron states at the Ge/HfO₂ interface is determined by combining the internal photoemission of electrons and holes from Ge into the Hf oxide and AC capacitance/conductance measurements. The inferred offsets of the conduction and valence band at the interface, i.e., 2.0 ± 0.1 and 3.0 ± 0.1 eV, respectively, suggest the possibility to apply the deposited HfO₂ layer as a suitable insulator on Ge. The post-deposition annealing of the Ge/HfO₂ structures in oxygen results in 1 eV reduction of the valence band offset, which is attributed to the growth of a GeO₂ interlayer. However, this treatment enables one to substantially reduce the density of Ge/HfO₂ interface traps, approaching ≈1×10¹² cm⁻² eV⁻¹ near the Ge midgap.