Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor

A compact, tunable CMOS transconductor is presented. The combined use of a Floating-Gate MOS (FGMOS) differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity. Measurement results for a prototype fabricated using a 0.8 m CMOS technology are provided, confirming on silicon the validity of the proposed approach.     

Very Low Voltage CMOS Current Multiplier with Floating DC Level Shifters

A compact, wide dynamic range, four-quadrant analog CMOS current multiplier is presented. The use of floating DC level shifters (floating batteries) made by resistors and current sources allows low supply voltages while maintaining at the same time a large input range and low harmonic distortion. Measurement results for an experimental prototype in a 0.8 m CMOS technology demonstrate on silicon the proposed technique.     

Very Low Voltage Rail-to-Rail Programmable-Gain CMOS Amplifier

A novel design technique for operating closed-loop amplifier circuits at very low supply voltages is proposed. It is based on the use of quasi-floating gate transistors, avoiding issues encountered in true floating-gate structures such as the initial floating-gate charge, offset drift with temperature, and the gain-bandwidth product degradation. A programmable-gain differential amplifier is designed and implemented following this method. Measurement results of an experimental prototype fabricated in a 0.5-m CMOS technology validate on silicon the proposed technique.     

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent corner error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 m CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.     

Low-Voltage Analog Circuits Based on Wideband Capacitive Coupling

A technique for wideband low-voltage analog circuit operation based on capacitive signal coupling is discussed. Circuits based on this technique do not show the GB degradation of other low-voltage approaches based on floating-gate transistors. The technique is validated with simulations of a new CMOS mixer and experimental results of a test chip in a 0.5 m CMOS technology.     

Systematic Design of Companding Systems by Component Substitution

A design method for externally linear, internally nonlinear systems is presented which allows them to be derived from externally equivalent systems in a systematic way and with a minimum synthesis effort, just performing a simple component-to-component substitution. As a particular case, the synthesis of the most popular versions of voltage companding systems from externally equivalent Gm-C systems is addressed. The practical design of companding systems based on the MOS square law (Square-Root Domain systems) is fully illustrated along the complete design flow, from the Gm-C prototype to silicon. These systems, feasible in CMOS technologies and formerly difficult to obtain due to the inherent complexity of existing synthesis methods, particularly benefit from the simplicity of the proposed approach. Experimental results for two versions of tunable Square-Root Domain biquadratic filters and oscillators thus obtained and fabricated in a 2.4-m CMOS process are presented, featuring favorable tunability and low THD.     

A CMOS Hearing Aid Device

In this paper a CMOS Hearing Aid Device is described. The system is composed of a low-distortion low-noise preamplifier, an automatic gain control (AGC), a fully programmable switched-capacitor filter (equalizer), and a control system. The device has been fabricated in a 1.2 m CMOS analog process. The dynamic range of the device is 55 dB while the harmonic distortion components are below –50 dB. Experimental results show the feasibility of the proposed architecture.     

A 2.4-GHz CMOS Monolithic VCO with an MOS Varactor

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8m CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about –118 dBc/Hz at 1 MHz from the carrier.     

High-Selectivity Switched-Capacitor Bandpass Filter with Quasi-Continuous Quality Factor Tunability

This paper describes the design and implementation of a second-order switched-capacitor (SC) bandpass (BP) filter with very wide quality factor (Q) programmability range. The filter selectivity is digitally programmed by varying the effective sampling frequency of an SC branch, without modifying any capacitor value. The proposed approach allows a quasi-continuous Q-factor tunability avoiding, in principle, the inherent quantization error associated to any traditional programming technique. Automatic Q-factor tuning is performed by using a scheme based on an amplitude-locking loop approach. Experimental results obtained from a 0.8-m CMOS integrated prototype demonstrate the versatility of the proposed technique for high-Q SC BP filters.     

A CMOS Four Quadrant Current/Transconductance Multiplier

This paper describes a highly linear current four quadrant multiplier. The circuit is designed to operate in a fully differential way. It is based on the square-law characteristic of MOS transistors in saturation region. Experimental results for 2 m CMOS technology are provided.     

The Concept of Operational Rank Extractor

An operational rank extractor (ORE) is introduced in this paper as an operational amplifier having rank extractors at its inputs. This versatile building block can implement a variety of nonlinear transfer functions such as a dead-zone amplifier, a limiter, a full-wave rectifier, and a tri-state comparator (including hysteretic behavior). A 6-input circuit has been implemented in a 2 m CMOS process. The total silicon area is 460 × 100m², and the circuit dissipates 0.7 mW from a single 5 V supply. Various circuit configurations are analyzed theoretically, and experimental results are also provided.     

Design Theory and Performance of 1-GHz CMOS Downconversion and Upconversion Mixers

A CMOS mixer topology capable of both downconversion and upconversion mixing for use in integrated wireless transceivers is presented. The mixing is based on two cross-coupled differential pairs as commutators with two source-followers as current modulators. Independence of the input and output bandwidths allows this topology to be optimized separately for either downconversion or upconversion mixer. The prototypes of both upconversion and downconversion mixers, optimized for linearity and realized in 0.8 m CMOS technology, have been demonstrated to fully operate at 1 GHz with good linearity and low power consumption. In addition, another mixer, optimized for noise figure and realized in 0.5 m CMOS technology, has been designed to achieve a NF of around 12 dB.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f _in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.     

Low-Voltage Low-Power Integrated Phase-Shifter as Resistive Sensor Transducer

In this paper, we present a CMOSlow-voltage low-power phase shiftertopology, to be used as an integratedresistive sensor interface for portableapplications. The circuit furnishes an outputsquare wave whose time delay and shift arelinear with the value of the sensorresistance. Shifter non-idealities havebeen also considered. The circuit can be alsotransformed into an oscillator by a simpleterminal connection. In this case, theoscillation frequency is inverselyproportional to the same resistance. The proposed topology has been designed andfabricated in CMOS Mietec 0.5 technologyand can operate at supply voltages lowerthan 3 V. The minimum operating supplyvoltage is 1.2 V, the power consumptionbeing only 1 W for the shifter. Thecircuit shows good insensitivity to both thesupply voltage and temperature variations,so it can be applied as an alternativetopology for portable-system integratedinterfaces for typical resistive sensors ofM range.     

A 3.3 V Power Feedback Chip for Linearization of RF Power Amplifiers

The power feedback technique is a simple and low cost linearization scheme suitable for consumer products such as hand sets. This paper presents a custom chip for linearization of RF power amplifiers using power feedback. The chip, implemented in a standard double-metal double-poly 0.6 m CMOS process, operates with 3.3 V supply voltage and consumes 62 mW. When it was used to linearize a commercially available high efficiency RF power amplifier at 850 MHz, experimental results showed that out-of-band power at 30 kHz offset was reduced some 10 dB for a /4-shifted DQPSK modulated North American digital cellular (NADC) signal. For the same level of adjacent channel interference (ACI), the efficiency was increased from 35% to 48%.     

A CMOS A/D Converter with Piecewise Linear Characteristic and Its Application to Sensor Linearization

A novel 8-bit CMOS A/D converter with piecewise linear characteristic is designed, implemented and tested. It can be regarded as a two-stage flash A/D converter. The resulting architecture can be applied to the linearization of nonlinear characteristics of a wide variety of sensors, just adapting the break points of the piecewise linear characteristic to get the best-fit approach to the inverse of the sensor characteristic under consideration. A very compact implementation is obtained, since two-stage A/D conversion and linearization are both performed simultaneously by the same circuit and because both A/D conversion stages share most of the required hardware. As a particular example, a sinusoidal nonlinearity, typical of several types of solid-state sensors, is compensated in this paper. Measurement results for a 2 m CMOS prototype demonstrate the validity of the proposed approach.     

A 1 V Second Order Sigma-Delta Modulator

A second order switched capacitor sigma-delta modulator operating at a supplyvoltage of 1 V is presented. This low supply voltage restricts the gate overdrivevoltage available for switching transistors. The design relies on the elimination ofcritical switches by using a modified switched op amp for the integrator and novelswitched half-supply and reference voltage generators. The design has been carried outin a fully differential configuration in order to minimize errors arising from chargeinjection and clock-feedthrough effects. The converter has been implemented using aconventional 0.8 m double-poly double-metal CMOS process, having a nominalthreshold voltage of 0.75 V. Test results, showing more than 9 bits of resolutionwith an oversampling ratio of 64, are also presented.     

A Novel Dual-Output CCII-Based Single-Ended to Differential Converter

In this paper a novel single-ended to differential converter topology, based on second generation current conveyors (CCIIs) is proposed. The converter architecture is very simple, being formed by a dual output current-conveyor (DOCCII) and three resistances which fix the gain of the circuit independently from the active block. Also the DOCCII topology is original, having the particular feature that output signals show a very little phase shifting between the two high impedance current outputs. The circuit has been implemented in a standard CMOS technology (AMS 0.35 m), using a supply voltage of ± 0.75 V. Theoretical values, circuit simulations and post-layout simulations are also shown and their good agreement confirms the validity of the presented idea.     

Design of a New High Speed Amplifier Circuit for the Analog Subsystems

A high speed CMOS amplifier circuit with a new architecture especially suited for analog subsystems and a simple high speed CMOS comparator utilizing the proposed CMOS amplifier circuit are presented. The proposed circuit is simulated using 0.35 m process parameters. The configuration results in several performance improvements over a typical CMOS differential to single ended amplifier. Design details and simulation results show that the newly designed CMOS amplifier circuit and the high speed CMOS comparator are applicable to high speed analog subsystems, especially the flash A/D converter.