84dB动态范围13b/400kHz/3V/5.88mW∑△模数转换器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现.电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm.调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW.测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB.     

80dB动态范围，用于低中频结构GSM接收机的ΣΔ调制器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器.该调制器采用3阶单环单比特的结构,电路使用全差分开关电容结构实现,并在0.6μm 2P2M CMOS工艺下流片验证.调制器使用全差分±1V参考电压,工作在26MHz采样频率,过采样率为64.测试结果表明,在200kHz信号带宽内,调制器达到80.6dB动态范围,峰值SNDR达到71.8dB,峰值SNR达到73.9dB.整个调制器电源电压为5V,静态功耗为15mW.     

一种13位400 kHz 11 mW Σ-Δ模拟/数字转换器

设计了应用于低中频GSM接收机的三阶单环单比特结构Σ-Δ A/D转换器。调制器采用全差分开关电容积分器实现。仿真结果显示,在工作电压为3 V、信号带宽200 kHz、0.35μm CMOS工艺的条件下,过采样率选择为64,信号/噪声失真比(SNDR)达到85 dB,功耗不超过11mW。     

一种13位400kHz1 1mW∑-△模拟／数字转换器

设计了应用于低中频GSM接收机的三阶单环单比特结构∑-△A／D转换器。调制器采用全差分开关电容积分器实现。仿真结果显示，在工作电压为3V、信号带宽200kHz、0．35μmCMOS工艺的条件下，过采样率选择为64，信号／噪声失真比（SNDR）达到85dB，功耗不超过11mW。     

80dB动态范围,用于低中频结构GSM接收机的∑△调制器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.该调制器采用3阶单环单比特的结构,电路使用全差分开关电容结构实现,并在0.6μm 2P2M CMOS 工艺下流片验证.调制器使用全差分±1V参考电压,工作在26MHz采样频率,过采样率为64.测试结果表明,在200kHz信号带宽内,调制器达到80.6dB动态范围,峰值SNDR达到71.8dB,峰值SNR达到73.9dB.整个调制器电源电压为5V,静态功耗为15mW.     

1.8V音频∑△调制器的设计

介绍了一种适用于语音信号处理的16位24 kHz ∑△调制器.该电路采用单环三阶单比特量化形式,利用Matlab优化调制器系数.电路采用SIMC 0.18μm CMOS工艺实现,通过Cadence/Spectre仿真器进行仿真.仿真结果显示,调制器在128倍过采样率时,带内信噪比达到107 dB,满足设计要求.     

1.8V音频Σ-Δ调制器的设计

介绍了一种适用于语音信号处理的16位24 kHzΣ-Δ调制器。该电路采用单环三阶单比特量化形式,利用Matlab优化调制器系数。电路采用SIMC 0.18μm CMOS工艺实现,通过Cadence/Spectre仿真器进行仿真。仿真结果显示,调制器在128倍过采样率时,带内信噪比达到107 dB,满足设计要求。     

80dB动态范围,用于低中频结构GSM接收机的∑△调制器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.该调制器采用3阶单环单比特的结构,电路使用全差分开关电容结构实现,并在0.6μm 2P2M CMOS 工艺下流片验证.调制器使用全差分±1V参考电压,工作在26MHz采样频率,过采样率为64.测试结果表明,在200kHz信号带宽内,调制器达到80.6dB动态范围,峰值SNDR达到71.8dB,峰值SNR达到73.9dB.整个调制器电源电压为5V,静态功耗为15mW.     

10 bit 20 MS/s流水线模数转换器设计

设计了一个20MHz采样率,10bit精度流水线模数转换器。采用新颖的栅压自举开关,使电路在输入信号频率很高时仍具有良好的动态性能;用MATLAB仿真增益增强型运算放大器在不同反馈因子下闭环零、极点特性,提出了使大信号建立时间最短的主运放、辅助运放单位增益带宽和相位裕度范围。采用SMIC0.35μm2P4M工艺流片验证,20MHz采样率,2.1MHz输入信号下,SFDR=73dBc,ENOB=9.18bit。     

一种带低失真采样开关的10位50MS/s采样保持电路

A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.     

High-Selectivity Switched-Capacitor Bandpass Filter with Quasi-Continuous Quality Factor Tunability

This paper describes the design and implementation of a second-order switched-capacitor (SC) bandpass (BP) filter with very wide quality factor (Q) programmability range. The filter selectivity is digitally programmed by varying the effective sampling frequency of an SC branch, without modifying any capacitor value. The proposed approach allows a quasi-continuous Q-factor tunability avoiding, in principle, the inherent quantization error associated to any traditional programming technique. Automatic Q-factor tuning is performed by using a scheme based on an amplitude-locking loop approach. Experimental results obtained from a 0.8-m CMOS integrated prototype demonstrate the versatility of the proposed technique for high-Q SC BP filters.     

A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps

A simple dynamic biasing scheme to extend the input/output range of cascode amplifiers is introduced. It requires minimum extra hardware and no additional power consumption. A dynamic biased telescopic op-amp is discussed as an application example. Experimental results of a fabricated test chip in 0.5 μm CMOS technology are presented that verify the proposed technique.     

Digital Technique for Instability Detection and Saturation Recovery in High-Order SC ΣΔ Modulators

Stability and saturation recovery are a key concern in High-order Switched Capacitor (SC) modulators, since they are conditionally stable architectures.A novel digital technique, which allows to detect instability in the digital domain, a fast recover of high-order modulators from instability and guarantees a minimum of Signal-to-Noise Ratio (SNR) also when the architecture gets unstable, is proposed. This technique operates in two steps: first, the instability is detected in the digital domain and the system is recovered to a proper operation and then a digital post-processing is performed in order to achieve a residual SNR also in the instability condition.This strategy has been applied to a 6th-order SC bandpass modulator operating at 42.8 MHz and featuring 74 dB Dynamic Range (DR) in a 200 kHz bandwidth. The benchmark modulator has been integrated in a standard double-poly 0.35 m 3.3 V CMOS technology with five metal layers.     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

Design tradeoffs for sub-mW CMOS biomedical limiting amplifiers

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35 μm CMOS technology to operate over dc to 20 MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280 μA from a 2-V supply and achieves a voltage gain of 72 dB.     

Very Low Voltage Rail-to-Rail Programmable-Gain CMOS Amplifier

A novel design technique for operating closed-loop amplifier circuits at very low supply voltages is proposed. It is based on the use of quasi-floating gate transistors, avoiding issues encountered in true floating-gate structures such as the initial floating-gate charge, offset drift with temperature, and the gain-bandwidth product degradation. A programmable-gain differential amplifier is designed and implemented following this method. Measurement results of an experimental prototype fabricated in a 0.5-m CMOS technology validate on silicon the proposed technique.