Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

A reconfigurable processor architecture combining multi-core and reconfigurable processing units

It’s a promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. Reconfigurable logic is separated into RPUs logically, which are coupled with general purpose cores as co-processors via a full crossbar switch. An RPU Manager (RPU-M) is also designed to manage RPUs. To verify RMC, a simulation method based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the evaluation accuracy of hardware function cores. Five workloads are selected to test RMC, including 3-DES, AES, SHA2, IDCT and JPEG_ENC. The experimental results show a 3.10 times average speedup over software implementation on the original multi-core, and the data and control communication overhead on RMC is acceptable.     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

一种新的基于可配置处理器的异构多核线程级动态调度模型

本文针对基于可配置处理器的异构多核结构,提出一种新的线程级动态调度模型。此类异构多核系统中每个核分别针对某一应用做指令集扩展,调度器通过线程、处理器核以及指令集间的映射关系,动态调度线程至适合的处理器核,从而在没有大幅增加芯片面积的前提下,达到与每个核都具有全扩展指令集相近似的加速比,此外该模型还可以有效减少编程模型的复杂度。     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

采用多核处理器进行可重构并行仿真的方法

文中对多传感器视觉信息处理算法进行分析,根据可重构处理器的并行计算参数模型提出了一种并行计算仿真的方法。多核处理器环境中,每个线程在独立的核上运行,线程间具有并发性。利用并发的线程模拟可重构阵列单元（PE）的运算方式,调用OpenMP设置多个线程并行执行,在多核计算机平台上模拟可重构处理器的计算过程。利用此方法能在没有具体的PE连接方案前,通过使用计算核模拟PE单元,将算法映射到多核处理器环境中。通过分析算法在多核计算机上的并发执行效率,来优化视觉信息算法在可重构阵列上的映射方案。     

Circuits and architectures for field programmable gate array with configurable supply voltage

Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused circuit elements can be power-gated. In this paper, we first design novel Vdd-programmable and Vdd-gateable interconnect switches with minimal number of configuration SRAM cells. We then evaluate Vdd-programmable FPGA architectures using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, our best architecture reduces the minimal energy-delay product by 54.39% with 17% more area and 3% more configuration SRAM cells. Our evaluation results also show that LUT size 4 gives the lowest energy consumption, and LUT size 7 leads to the highest performance, both for all evaluated architectures.     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

A mixed-signal BiCMOS front-end signal processor for high-temperature applications

A mixed-signal ASIC that implements an ultrasound front-end receiver in a 0.6 /spl mu/m BiCMOS HotASIC technology that features metal/metal capacitors and poly1/poly2 resistors is described. The ASIC includes a low-noise amplifier (LNA), a programmable gain amplifier (PGA), an output differential amplifier (ODA), and a second-order sigma-delta modulator (SDM), and is the most compact system for high-temperature ultrasound applications reported in literature. The circuit has a programmable gain and is designed for measuring the signal response (200 kHz to 700 kHz) from an ultrasound transducer. At 48 MHz clock frequency and 200/spl deg/C, the power consumption is 85 mW from a single 5 V supply. The die area of the chip is 5.52 mm/sup 2/.     

An analog DFE for disk drives using a mixed-signal integrator

An analog adaptive decision-feedback equalizer (DFE) is described. The DFE cancels intersymbol interference using four feedback taps, and a fifth tap cancels dc offset. The coefficient for each tap is adapted using a small mixed-signal integrator. The DFE dissipates 220 mW at a data rate of 150 Mb/s. The active area is 1.8 mm² in a 1-μm CMOS process     

A 1-V heterogeneous reconfigurable DSP IC for wireless basebanddigital signal processing

A heterogeneous reconfigurable platform enables the flexible implementation of baseband wireless functions at energy levels between 10 and 100 MOPS/mW, six times higher than traditional digital signal processors. A 5.2 mm×6.7 mm prototype processor, targeted for voice compression, is implemented in a 0.25-μm 6-metal CMOS process, and consumes 1.8 mW at an average operation rate of 40 MHz. It combines an embedded microprocessor with an array of computational units of different granularities, connected by a hierarchical reconfigurable interconnect network     

A unified reconfigurable CORDIC processor for floating-point arithmetic

ABSTRACT

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximises the sharing of common hardware circuit and achieves the area-delay efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 16384 × 16384 points target synthetic aperture radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T field programmable gate array platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.     

粗粒度可重构结构的性能估计方法

在设计初期,估计粗粒度可重构结构的性能,对粗粒度可重构结构设计具有指导意义.在考虑局部数据存储器结构以及局部数据存储器与可重构阵列的接口结构的情况下,建立了粗粒度可重构结构的参数模型,使用改进的螺旋形绑定策略将应用算法DFG(Data Flow Graph)中的算子绑定到可重构阵列的处理单元上,提出了一种粗粒度可重构结构的性能估计方法.应用实例表明,在设计初期,该方法能得到周期精确的估计结果,有效地指导粗粒度可重构结构的设计.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

A programmable image processing system using FPGAs

Real-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This piper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.     

A nonvolatile analog programmable voltage source using the VIPMOSEEPROM structure

A programmable voltage source using the vertical injection punchthrough based MOS (VIPMOS) EEPROM structure is presented. The circuit operates at a single 5-V supply and the output voltage is continuously available even during programming. The effect of programming is linearly dependent on the programming time. During programming no crosstalk from the enable pulses and only a little crosstalk from the program current are observed. If a decreasing program current is used, the output of the circuit can be set to its desired value without the need of an iterative program process     

Design methodology for configurable analog to digital conversion using support vector machines

We apply a support vector machine (SVM) classifier to the design of analog to digital converters. Each output bit of the converter is the output of a binary classifier, which is a nonlinear SVM. The classifier effectively learns a folding characteristic for each bit, which is realized as the weighted sum of a set of kernel functions. In our proposal, the kernel does not need to be symmetric or positive definite, unlike in the case of a conventional SVM. This makes the approach more amenable to VLSI design, where such constraints are hard to satisfy. The SVM uses a set of binary weights, which allows the folding characteristics to be digitally corrected after fabrication. This facility is of considerable value in analog design in a deep sub micron era, where simulation models do not adequately capture the behavior of devices, or their variations. The proposed methodology reduces design time, can be automated and calibrated for process variations and ageing, by changing a set of digital scaling coefficients.     

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35 μm CMOS is presented.The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF).The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications.In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide-10 to +40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA,and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.     

基于WLAN，WCDMA，和Bluetooth标准的可配置模拟基带处理电路

采用0.35μm工艺实现了一种基于WLAN、WCDMA和Bluetooth通信标准的可配置模拟基带处理电路。电路由两个级联的可变增益放大器和一个Gm-C椭圆低通滤波器组成。滤波器阶数和截止频率可调以满足不同应用的要求。更为重要的是,为了优化功耗,可变增益放大器的带宽可以动态调节,而且一些Gm单元在特定的应用下可以关断。所以,在3V电源电压下,模拟基带处理电路工作于WLAN标准模式时消耗了16.8mW的功耗,工作于WCDMA标准模式时消耗了8.9mW的功耗,而工作于Bluetooth标准模式时仅消耗了6.5mW的功耗。模拟基带处理电路可以提供-10~ +40dB的可变增益,同时针对Bluetooth、WCDMA、WLAN标准分别提供1MHz带宽的3阶低通滤波、2.2MHz带宽的4阶低通滤波和11MHz带宽的5阶低通滤波功能。     

A programmable analog CMOS synapse for neural networks

This paper presents a programmable analog synapse for use in both feedforward and feedback neural networks. The synapse consists of two complementary floating-gate MOSFETs which are programmable in both directions by Fowler-Nordheim tunneling. The P-transistor and the N-transistor are programmable independently with pulses of different amplitude and duration, and hence finer weight adjustment is made possible. An experimental 4×4 synapse array has been designed, which in addition has 32 analog CMOS switches and x–y decoders to select a synapse cell for programming. It has been fabricated using a standard 2-m, double-polysilicon CMOS technology. Simulation results confirm that output current of synapse is proportional to the product of the input voltage and weight and also shows both inhibitory and excitatory current. Current summing effect has been observed at the input of a neuron. This array is designed using modular and regular structured elements, and hence is easily expandable to larger networks.