1/f noise reduction in PMOSFETs by an additional preoxidationcleaning with an ammonia hydrogen peroxide mixture

1/f noise magnitude in a 15 μm×0.5 μm PMOSFET was remarkably reduced by simply adding a cleaning step using an ammonia hydrogen peroxide mixture (APM) prior to gate oxidation. Gate input-referred noise level for APM-finished PMOSFETs at f=10 Hz was around -128 dBV²/Hz whereas for standard, HF-finished devices, the level was around -114 dBV²/Hz. Flat-band voltages (V_FBs) determined by a capacitance-voltage (C-V) measurement were -0.19 V for an APM-finished PMOS and -0.34 V for a HF-finished PMOS. Based on the V_FB values, interface state densities were determined to be N_it=3.02×10¹¹ cm^-2 for APM-finished PMOS and N_it=6.47×10¹¹ cm^-2 for HF-finished PMOS. Lower interface state density obtained by the APM preoxidation cleaning is consistent with the remarkable reduction in the 1/f noise magnitude     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO     

Ion-implanted high microwave power indium phosphide transistors

Encapsulated rapid thermal annealing (RTA) has been used in the fabrication of indium phosphide (InP) power metal-insulator-semiconductor field-effect transistors (MISFETs) with ion-implanted source, drain, and active channel regions. The MISFETs had a gate length of 1.4 μm. Six to ten gate fingers per device, with individual gate finger widths of 100 or 125 μm, were used to make MISFETs with total gate widths of 0.75, 0.8, or 1 mm. The source and drain contact regions and the channel region of the MISFETs were fabricated using silicon implants in semi-insulating InP at energies from 60 to 360 keV with doses from 1×10¹² to 5.6×10¹⁴ cm^-2. The implants were activated using RTA at 700°C for 30 s in N₂ or H₂ ambients using a silicon nitride encapsulant. The high-power, high-efficiency MISFETs were characterized at 9.7 GHz, and the output microwave power density for the RTA conditions used was as high as 2.4 W/mm. For a 1-W input at 9.7 GHz gains up to 3.7 dB were observed, with an associated power-added efficiency of 29%. The output power density was 70% greater than that reported for GaAs MESFETs     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively     

Gate oxide integrity of thermal oxide grown on high temperatureformed Si0.3Ge0.7

We have investigated the gate oxide integrity of thermal oxides direct grown on high temperature formed Si_0.3Ge_0.7. Good oxide integrity is evidenced by the low interface-trap density of 5.9×10¹⁰ eV^-1 cm^-2, low oxide charge density of -5.6×10¹⁰ cm^-2, and the small stress-induced leakage current after -3.3 V stress for 10 000 s. The good gate oxide integrity is due to the high temperature formed and strain-relaxed Si_0.3Ge_0.7 that has a original smooth surface and stable after subsequent high temperature process     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

Bulk and surface properties of amorphous hydrogenated fluorinatedsilicon grown from SiF4 and H2

A detailed study of the growth of amorphous hydrogenated fluorinated silicon (a-Si:H, F) from a DC glow discharge in SiF₄ and H₂ is discussed. The electrical properties of the films can be varied over a very wide range. The bulk properties of the best films that were measured included an Urbach energy E_u =43 meV, a deep-level defect density N_s=1.5×10¹⁵ cm^-3, and a hole drift mobility of 8×10^-3 cm² V^-1 s^-1, which reflects a characteristic valence band energy of 36 meV. It was found that E_u, N _s, and the density of surface states N_ss are related to each other. Under the deposition condition of the films with the best bulk properties, N_ss reaches its highest value of 1×10¹⁴ cm^-2. It is suggested that in growth from SiF₄/H₂, the density of dangling bonds at the growing surface is very sensitive to the deposition conditions     

Dependence of electron channel mobility on Si-SiO2interface microroughness

The effect of the Si-SiO₂ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH₄ OH in the NH₄OH-H₂O₂-H₂O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO₂ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm²/V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5×10¹⁷ cm^-3, i.e. the electron bulk mobility is 400 cm²/V-s. It goes down to 100 cm²/V-s when the interface microroughness exceeds 1 nm     

Thin oxide thickness extrapolation from capacitance-voltagemeasurements

Five oxide-thickness extrapolation algorithms, all based on the same model (metal gate, negligible interface traps, no quantum effects), are compared to determine their accuracy. Three sets of parameters are used: (acceptor impurity concentration, oxide thickness, and temperature): (10¹⁶ cm^-3, 250 Å, 300 K), (5×10¹⁷ Cm^-3, 250 Å, 300 K), and (5×10¹⁷ cm^-3, 50 Å, 150 K). Demonstration examples show that a new extrapolation method, which includes Fermi-Dirac statistics, gives the most accurate results, while the widely-used C_o≃C_g (measured at the power supply voltage) is the least accurate. The effect of polycrystalline silicon gate is also illustrated     

Measurements and modeling of MOSFET I-V characteristics withpolysilicon depletion effect

The authors study the degradation of MOSFET current-voltage (V-I) characteristics as a function of polysilicon gate concentration (N_p ), oxide thickness (t_ox) and substrate impurity concentration (N_D) using measured and modeled results. Experimentally it is found that for MOSFETs with thin gate oxide (t_ox≈70 Å) and high substrate concentration (N_D ≈1.6×10¹⁷ cm^-3) the reduction in the drain current I_DS can be as large as 10% to 20% for devices with insufficiently doped polysilicon gate (5×10¹⁸ ⩽N_p⩽1.6×10¹⁹ cm^-3). Theoretically it is shown that the drain current degradation becomes more pronounced as N_p decreases, t_ox decreases, or N_D, increases. A modified Pao-Sah model that takes into account the polysilicon depletion effect and an accurate gate-field-dependent mobility model are used to compute I-V characteristics for various values of N_p, t_ox, and N_D. Good agreement between experimental and modeled results is observed over a wide range of devices     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

Heterostructure devices using self-aligned p-type diffused ohmiccontacts

Describes the use of a p-type refractory ohmic contact in ohmic self-aligned devices. The contacts are based on self-aligned diffusion of zinc-doped tungsten film. The diffusion is nearly isotropic in the vicinity of silicon nitride sidewalls, allowing self-alignment of ohmic contacts with emitters and gates. Low-resistance contacts (<10^-6 Ω·cm²) are formed both to GaAs and GaAlAs, and the lifetime of the diffused region is superior to that obtained from implantation. Heterostructure bipolar transistors (HBTs) showing high current gains (⩾50 at 2×10³ A·cm^-2 and ⩾200 at 1×10⁵ A·cm^-2 with micrometer-sized emitter widths) and p-channel GaAs gate heterostructure field-effect transistors (HFETs) showing high transconductances (78 mS/mm at 2.2-μm gate length) have been fabricated using this contact     

Delta-doped AlGaN/AlN/GaN microwave HFETs grown by metalorganicchemical vapour deposition

The performance of an innovative delta-doped AlGaN/AlN/GaN heterojunction field-effect transistor (HFET) structure is reported. The epitaxial heterostructures were grown on semi-insulating SiC substrates by low-pressure metalorganic chemical vapour deposition. These structures exhibit a maximum carrier mobility of 1058 cm²/V s and a sheet carrier density of 2.35×10¹³ cm^-2 at room temperature, corresponding to a large n_s μ_n product of 2.49×10¹⁶ V s. HFET devices with 0.25 μm gate length were fabricated and exhibited a maximum current density as high as 1.5 A/mm (at V_G=+1 V) and a peak transconductance of g_m=240 mS/mm. High-frequency device measurements yielded a cutoff frequency of f_t≃50 GHz and maximum oscillation frequency f_max≃130 GHz     

The characteristics of CMOS devices in oxygen-implantedsilicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25×10¹⁸ cm^-2 to 1.4×10¹⁸ cm^-2 . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4×10¹⁷ cm^-2 oxygen dose and annealed at 1150°C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal