The Design of a 2-V 900-MHz CMOS Bandpass Amplifier

A 900 MHz low-power CMOS bandpassamplifier suitable for the applications of RFfront-end in wireless communication receiversis proposed and analyzed. In this design, thetemperature compensation circuit is used tostabilize the amplifier gain so that theoverall amplifier has a good temperaturestability. Moreover, the compact tunablepositive-feedback circuit is connected to theintegrated spiral inductor to generate thenegative resistance and enhance its value. The simple diode varactor circuit isadopted for center-frequency tuning. These twoimproved circuits can reduce the powerdissipation of the amplifier. An experimentalchip fabricated by 0.5 mdouble-poly-double-metal CMOS technologyoccupies a chip area of ; chip area. The measuredresults have verified the performance of thefabricated CMOS bandpass amplifier. Under a2-V supply voltage, the measured quality factoris tunable between 4.5 and 50 and the tunablefrequency range is between 845 MHz and 915 MHz. At , the measured is 20 dB whereas thenoise figure is 5.2 dB in the passband. Thegain variation is less than 4 dB in the rangeof 0–80^°C. The dc powerdissipation is 35 mW. Suitable amplifier gain,low power dissipation, and good temperaturestability make the proposed bandpass amplifierquite feasible in RF front-endapplications.     

Current-Mode High Output Impedance Multifunction Filters Employing Minimum Number of FTFNs

In this study, five current-mode FTFN-based multifunction filters are proposed, which realize the same transfer functions in ideal case. All circuits employ two capacitors and three resistors. For each circuit R-C:C-R transformation increases the number of realization possibilities to ten. The proposed topologies simultaneously realize three basic filtering functions using minimum number of FTFNs and provide high output impedances that enable easy cascading in current mode. Sensitivity analysis of the filters show that they have low passive sensitivities, and of the filters are insensitive to current tracking errors, furthermore of the filters are insensitive to voltage tracking errors of the FTFNs. The proposed circuits do not require component matching condition except for notch and allpass responses and permit independent adjustment of without disturbing . Experimental and simulation results are given to verify the theoretical analyses.     

Statistical Design of the Four-MOSFET Structure

The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor and values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.     

A Symbolic Circuit Analysis-Oriented Algorithm for Finding a Common Tree of the Current and Voltage Graphs

A fundamental problem of symbolic analysis of electric networks when using the signal-flow (SFG) graph method is to find the common tree of the current and voltage graph ( and , respectively). In this paper we introduce a novel method in order to determine a common tree of both graphs, which may be used to obtain the symbolic network transfer function when carrying out the small-signal analysis of linear(ised) circuits.     

A Small Area Charge Sensitive Readout Chain with a Dual Mode of Operation

A charge sensitive readout chain has been designed and fabricated in acommercially available 0.8 m CMOS technology. The readout chain is optimizedfor pixel detectors measuring soft X-ray energies up to 20 KeV. In the first modean analog signal proportional to input charge is generated and processed in realtime. In the second mode a peak-and-hold operation is enabled and therelevant signal is processed in later time. This dual mode of operation iscontrolled by an external digital signal. The readout chain consists of a chargeamplifier, a shaper, an operational amplifier which can either operate as avoltage amplifier or a peak detector and an output buffer. Its area is . The gain at the shaper output is 378 mv/fC, theENC is 16 rms at 160 nsec shaping time. The overall gainis 557 mV/fC, the ENC is rms with 240 nsec peaking timeand 1.4 sec recovery time. The overall power dissipation is 1.5 mWatt with aload capacitance of 25 pF.     

A 5.8 GHz Low Noise Amplifier for Wireless LAN Applications in Silicon Bipolar Technology

A monolithic integrated low-noise amplifier for operation in the 5.8-GHzband is described. Two different versions have been implemented where the biasing wasadapted to allow operation over a different range of supply voltage. At 5-V, theamplifiers gain is about 17-dB, with a noise figure of 4.2-dB and 1-dB compressionpoint at –15-dBm input power. The circuits have been designed utilizing a0.6-micron silicon bipolar production technology, featuring npn transistors with and of about20-GHz.     

A DDS Synthesizer with Digital Time Domain Interpolator

A DDS type circuit structure for producing numericallyprogrammable square wave clock signal is presented. The high speed D/Aconverter needed in conventional DDS systems is replaced by an tap delay line time domain interpolator thateffectively increases the sampling rate by a factor of . Thus the circuit can be used up to full clock rate withoutimage filtering. A prototype IC with clock frequency of 30 MHz, 5 bitinterpolator and SFDR of –40 dBc up to 10 MHz and –33 dBcup to 15 MHz has been designed and tested.     

On the Scalability of 2-D Discrete Wavelet Transform Algorithms

The ability of a parallel algorithm to make efficient use of increasing computational resources is known as its scalability. In this paper, we develop four parallel algorithms for the 2-dimensional Discrete Wavelet Transform algorithm (2-D DWT), and derive their scalability properties on Mesh and Hypercube interconnection networks. We consider two versions of the 2-D DWT algorithm, known as the Standard (S) and Non-standard (NS) forms, mapped onto P processors under two data partitioning schemes, namely checkerboard (CP) and stripped (SP) partitioning. The two checkerboard partitioned algorithms (Non-standard form, NS-CP), and as (Standard form, S-CP); while on the store-and-forward-routed (SF-routed) Mesh and Hypercube they are scalable as (NS-CP), and as (S-CP), respectively, where M ² is the number of elements in the input matrix, and (0,1) is a parameter relating M to the number of desired octaves J as . On the CT-routed Hypercube, scalability of the NS-form algorithms shows similar behavior as on the CT-routed Mesh. The Standard form algorithm with stripped partitioning (S-SP) is scalable on the CT-routed Hypercube as M ² = (P ²), and it is unscalable on the CT-routed Mesh. Although asymptotically the stripped partitioned algorithm S-SP on the CT-routed Hypercube would appear to be inferior to its checkerboard counterpart S-CP, detailed analysis based on the proportionality constants of the isoefficiency function shows that S-SP is actually more efficient than S-CP over a realistic range of machine and problem sizes. A milder form of this result holds on the CT- and SF-routed Mesh, where S-SP would, asymptotically, appear to be altogether unscalable.     

A Fully Integrated, Low Noise and Low Power BiCMOS Front-end Readout System for Capacitive Detectors

Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (rms) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1 fC) with non-linearity of less than 3% and linear input dynamic range is MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of pions/cm² are also presented in this paper.     

Optimizing CMOS Transconductor-C Filters for Low Power Wide Band Operation

A novel figure of merit to describe the bandwidth power efficiency of CMOS transconductors— is proposed and optimized for cross-coupled differential pair transconductor structures. The optimization is done in two different ways: univariable unconstrained and multivariable constrained. It is revealed that not only dc biases but also ac input phases can affect the bandwidth power efficiency of the transconductor. The bias voltages which can lead to best ratio at different ac phase combinations are obtained and presented in the article. HSPICE simulations are conducted to verify the theoretical predictions. On the basis of the cross-coupled differential pair transconductor, a biquadratic transconductor-C filter configuration is implemented. The frequency vs. power characteristic of the filter is studied for both optimally- and non-optimally-biased transconductor. It is shown that the optimization of the transconductor structure can result in performance improvement of the transconductor-C filter. The deviation of the optimal bias condition between the transconductor alone and the transconductor-C filter due to the inclusion of peripheray circuitries in the filter is discussed in the article.     

A Low-Power Block-Matching Cell for Video Compression

This paper describes theimplementation of a block-matching modulewith digital I/O. Algorithmic analysisdemonstrates that the precisionrequirements can be met by a compactcircuit that processes the signal in thecharge domain. The required conversionbetween voltages and charges is achieved byMOS capacitors. As a result, it can befabricated by any inexpensive digital CMOStechnology. A test chip has beenimplemented in a standard CMOS 1.6 mtechnology and the measured energyconsumption is 1.2 nJ per block match usingan pixel matrix. Simulations ofthe same cell in 0.35 m and 0.25 mCMOS technology are presented, showing thescalability of the approach.     

Finite-Memory Systems

Let K be a field, k and n positive integers and let matrices with coefficients in K. For any function

Generalization of a Theorem for Replacing CCIIs by CFOAs in Current-Mode Circuits

A current feedback op-amp (CFOA) has the advantage that feedback structures in current-mode circuits are more easily devised because the voltage buffer at the output of the CFOA does not load the output of the integral positive, second-generation current conveyor (CCII⁺) that constitutes part of the CFOA. In this paper, the changes on the current mode transfer function of a linear circuit composed of a subnetwork connected to a CCII⁺ are determined when the CCII⁺ is replaced by a CFOA and a feedback component is connected from the output of the CFOA to an independent node of . Two applications of the results are provided. A new theorem is then presented which generalizes the results. This theorem should be useful for the comparison, synthesis, and improvement of linear current-mode signal processing circuits.     

Optimizing Elliptic Filter Selectivity

The problem of determining the band-edge selectivity of elliptic filters and its optimization in filter design is considered. The band-edge selectivity is derived with respect to the -th order elliptic function. The selectivity formula embodies potential trade-offs in filter requirements for improving filter mangitude or delay response. Design examples are submitted in support of the theory. A simple proof describes the Chebyshev filter as an elliptic filter in the limit of infinite stopband corner frequency.     

A Low-Power 100 MHz Analog FIR Filter for PRML Equalization

This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-m CMOS technology and consumes power of 200 mW for V power supply voltage.     

BIBO Stability of D-Dimensional Filters

Consider the class of d-dimensional causal filters characterized by a d-variate rational function analytic on the polydisk . The BIBO stability of such filters has been the subject of much research over the past two decades. In this paper we analyze the BIBO stability of such functions and prove necessary and sufficient conditions for BIBO stability of a d-dimensional filter. In particular, we prove if a d-variate filter H(z) analytic on has a Fourier expansion that converges uniformly on the closure of , then H(z) is BIBO stable. This result proves a long standing conjecture set forth by Bose in [3].     

Pn Photodiodes for Pulsed Laser Rangefinding Applications Realized in Standard CMOS/BiCMOS Processes

This paper describes simulation of theoperation of integrated high-speed photodiodes and verification of the results bymeans of measurements performed with two typesof photodiode, one implemented in a standard 0.8m CMOS process and the other in a standard1.2 m BiCMOS process. The measured rise timesand responsivities of the photodiodes were <5ns and 0.28 A/W in the CMOS process and 30 ns and0.31 A/W in the BiCMOS process. Furthermore, thesuitability of the photodiode for 3D vision wasinvestigated by designing an array ofphotodetectors and measuring the isolationbetween the detector blocks. The results confirmthat the photodetectors and receiver for a pulsedlaser rangefinder can be implemented on the samechip in a standard process without any processmodifications.     

Synthesis of Time Delay Networks Approximating the Pulse Response Described by an Integer Power of a Sinusoid Over Its Semi-Period

The paper describes the time delay network synthesis using a special approximation of network pulse response. One starts by choosing the pulse response as a delayed semi-period of an -th power of sinusoid. The Laplace transform of this pulse is a transcendental function. The real and imaginary parts of this function may be expanded into infinite products. Then, approximating these expansions by finite amount of terms one can obtain the network transfer function realizable by a reactance network loaded with a resistor. Design examples for differently delayed sine-squared pulse response are given.     

Linear phase FIR approximation of magnitude response |1/ω| for maximal flatness at an arbitrary frequency ω0, 0<ω0<π*

In many signal processing situations, the desired (ideal) magnitude response of the filter is a rational function: (a digital integrator). The requirements of a linear phase response and guaranteed stable performance limit the design to a finite impulse response (FIR) structure. In many applications we require the FIR filter to yield a highly accurate magnitude response for a narrow band of frequencies with maximal flatness at an arbitrary frequency ₀ in the spectrum (0, ). No techniques for meeting such requirements with respect to approximation of are known in the literature. This paper suggests a design by which the linear phase magnitude response can be approximated by an FIR configuration giving a maximally flat (in the Butterworth sense) response at an arbitrary frequency ₀, 0<₀<^*. A technique to compute exact weights for the design has also been given.