A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

A novel full-wave rectifier/sinusoidal frequency doubler topology based on CFOAs

In this paper, a high-efficiency class-F power amplifier (PA) is designed using integration between a low voltage p-HEMT transistor and a miniaturized microstrip suppressing cell. It results in nth harmonic suppression and high power added efficiency (PAE) under low radio frequency (RF) input powers. The simulation is performed based on harmonic balance analysis. The proposed power amplifier is fabricated, and measurements results validated the simulations. The proposed power amplifier operates at 1.8 GHz with 100 MHz bandwidth and an average PAE of 71.1%, with very low drain voltage of 2 V. At fundamental frequency of 1.8 GHz, the maximum measured PAE is 73.5% at about 12 dBm RF input power. The maximum output power and gain are 23.4 and 17.5 dBm in RF input power ranges of 0–12 dBm, respectively. The fabricated class-F PA with such characteristics can be used for power amplifications in wireless transmitters such as 4G (4th generation)-LTE (long term evolution) communication systems.     

2 V-operated InGaP-AlGaAs-InGaAs enhancement-mode pseudomorphic HEMT

A low-voltage single power supply enhancement-mode InGaP-AlGaAs-InGaAs pseudomorphic high-electron mobility transistor (PHEMT) is reported for the first time. The fabricated 0.5/spl times/160 /spl mu/m/sup 2/ device shows low knee voltage of 0.3 V, drain-source current (I/sub DS/) of 375 mA/mm and maximum transconductance of 550 mS/mm when drain-source voltage (V/sub DS/) was 2.5 V. High-frequency performance was also achieved; the cut-off frequency(F/sub t/) is 60 GHz and maximum oscillation frequency(F/sub max/) is 128 GHz. The noise figure of the 160-/spl mu/m gate width device at 17 GHz was measured to be 1.02 dB with 10.12 dB associated gain. The E-mode InGaP-AlGaAs-InGaAs PHEMT exhibits a high output power density of 453 mW/mm with a high linear gain of 30.5 dB at 2.4 GHz. The E-mode PHEMT can also achieve a high maximum power added efficiency (PAE) of 70%, when tuned for maximum PAE.     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

基于器件特性的改进高效率F类微带拓扑分析与实现

本文提出了一种新型的F类高效率功率放大器微带匹配拓扑。该拓扑简单紧凑且考虑了功率三极管输出端寄生效应,使得F类设计理论分析更贴合实际。基于提出的拓扑结构,采用商用10W GaN HEMT(Gallium-Nitrogen High Electron Mobility Transistor)进行了仿真与硬件实现。测试结果表明:当漏极偏置27V,工作频率2.995GHz时,实测输出功率为37.3dBm,功率附加效率为72.9%。在15~30V的偏置范围内,漏极调制效率达到68.9%以上。实测与仿真结果的吻合,很好的验证了拓扑的可行性。     

串联偏置迭堆式毫米波功率放大器的设计

设计了一种串联迭堆式偏置供电的毫米波功率放大器,其漏极供电电压高达+24V。该功率放大器共包含4个单芯片功率放大模块,每个模块承受+6V左右漏极电压。功率合成网络采用一分四的E面波导功分器,模块与功分网络间相互绝缘连接。该功率放大器最终实现的性能指标是:在直流偏置点(+24V,4.2A)条件下,功率放大器在频段26～30GHz内其连续波饱和输出功率大于42.1dBm,功率附加效率大于11.0%。提出了一种毫米波发射机功率输出部分新的构架形式,在模块级别对功率放大器串联馈电进行了首次尝试。     

CMOS RF Power Amplifier for UHF Stationary RFID Reader

A CMOS power amplifier (PA) for a UHF (860–960 MHz) stationary RFID reader is presented. To design a high power and power efficient CMOS PA, quasi four pair structure and integrated passive device (IPD) transformers are used. An amplitude modulation is performed through the cascode gate with a pulse shaping filter. The chips are fabricated in a 0.18 $mu$m CMOS process and IPD. Measurements show output power of 32.8–33.37 dBm and the power added efficiency (PAE) of 51.8–56.1% with the supply voltage 3.0 V.      

A 2.4-GHz SiGe HBT power amplifier with bias current controlling circuit

A 2.4-GHz SiGe HBT power amplifier (PA) with a novel bias current controlling circuit has been realized in IBM 0.35-μm SiGe BiCMOS technology, BiCMOS5PAe. The bias circuit switches the quiescent current to make the PA operate in a high or low power mode. Under a single supply voltage of 3.5 V, the two-stage mode-switchable power amplifier provides a PAE improvement up to 56.7% and 19.2% at an output power of 0 and 20 dBm, respectively, with a reduced quiescent current in the low power mode as compared to only operating the PA in the high power mode. The die size is only 1.32 × 1.37 mm2.     

An improved 860–960 MHz fully integrated CMOS power amplifier designation for UHF RFID transmitter

An improved design of 860–960 MHz fully integrated CMOS power amplifier (PA) for UHF RFID transmitter is presented in this paper. It utilizes three stage differential structure, including common-source structure applying RC feedback circuit to improve linearity, cascade structure adopting self-biased cascode technique and self-forward-body-bias (SFBB) technique to overcome shortcomings of low breakdown voltage and to reduce supply voltage respectively in order to obtain high output power, high efficiency and low supply voltage. By integrating these techniques organically, simulation results demonstrate that the circuit provides 21 dBm output power and 35% power-added efficiency (PAE) with 3 V supply. A comparison with other PAs operating in similar frequencies shows the proposed LNA has advantages of higher output power, higher PAE, higher linearity and lower supply voltage.     

A Highly Efficient and Linear Class-AB/F Power Amplifier for Multimode Operation

The class-AB/F power amplifier (PA), a multimode PA, which can operate at both class-AB and class-F modes, is analyzed and compared with the conventional class-F and class-AB PAs. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. To demonstrate the multimode PA, the PA is implemented using an InGaP/GaAs HBT process and it is tested with reverse-link IS-95A code division multiple access (CDMA) and PCS1900 global system for mobile communications signals in the personal communications service band. The class-AB operation for a CDMA signal delivers a power-added efficiency (PAE) of 38.9% and an adjacent channel power ratio of 49.5 and 56.5 dBc at the offset of 1.25 and 2.25 MHz, respectively, at the output power of 28 dBm. The maximum PAE of 64.7% under the class-F operation is measured at 32.5-dBm output power for a GSM signal. The class-AB/F PA is a good candidate for the multimode PA of next-generation wireless communication systems.     

Highly efficient double-doped heterojunction FET's forbattery-operated portable power applications

Microwave power performance of double-doped AlGaAs-InGaAs-AlGaAs heterojunction field-effect transistors (HJFET's) operated at a drain bias of 3 V is described. The fabricated 1.0 μm gate-length HJFET exhibited a maximum drain current of 500 mA/mm, a transconductance of 300 mS/mm, and a gate-to-drain breakdown voltage of 10 V. Power performance for a 14 mm gate periphery device demonstrated a maximum output power of 1.7 W with a 66% power-added efficiency (PAE) at 900 MHz. When the device was tuned for a maximum PAE, it delivered a 71% PAE with an output power of 1.2 W. The results indicate that the developed HJFET has great potential for 3 V battery-operated portable power applications     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

High Efficiency Linear Power Amplifier for IEEE 802.11g WLAN Applications

This letter presents the power amplifier (PA) design for IEEE 802.11g WLAN applications by using InGaP/GaAs heterojunction bipolar transistors (HBTs) with the dual bias network as the linearizer to improve the output power capability and linearity. The final designed PA utilizes a 3.3-V supply voltage producing a good power-aided-efficiency (PAE) in 39.3% with 26.5-dBm output power and 18.1-dB gain for a 2.4-GHz OFDM/64-QAM stimulus, while the error vector magnitude (EVM) is maintained at 4.9%, satisfying the standard specifications.     

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P_{1 dB} and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P_{1 dB}, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

Linearity optimizing on HBT power amplifier design

Highly linearized of HBT power amplifier (PA) was achieved for wireless digital mobile communication systems. This study investigates in detail the improvement of the linearity of HBT power amplifiers. The dependence of collector–base capacitance (C_bc) on bias is regarded initially as a trade-off between linearity and breakdown voltage. A simulation of device performed using SILVACO software reveals that at a capacitance ratio; C_bc (0/6 V) is 1.25 at a BV_ceo of 22 V. The device-level DC characteristic, load-pull power performance and power cell PAs are evaluated. A reasonably high PAE ~55% is attainable at 2.0 GHz and an adjacent channel leakage power ratio (ACPR) of over −48 dBc is achieved. The maximum achievable PAE is 54% with a maximum power density of 0.75 W/mm at 5.8 GHz. The novel HBT epitaxial structure, the layout of power cell design and the thick metal shunt process used to ensure the high linearity of the power cell are demonstrated.     

A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

This paper describes circuit design and measurement results of our newly developed InGaP/GaAs-HBT MMIC power amplifier (PA) module which can operate with 2.4-V low reference and low supply voltages of its on-chip bias circuits. To achieve the low-reference voltage operation, the following two new circuit design techniques are incorporated into the power amplifier: 1) AC-coupled, divided power stage configuration with two different kinds of bias feeding (voltage and current drive and only current drive) and 2) successful implementation of a diode linearizer built in the power stage. Theses two techniques allow the PA to offer smooth output transfer characteristics over a wide temperature range. Measurement results done under the conditions of 900 MHz, a 3.5-V collector voltage for power stage, and 2.4-V reference and collector voltages for the bias circuits show that the PA module meets J-/W-CDMA power and distortion requirements sufficiently over a wide temperature range from -10degC to 90degC while keeping a low quiescent current of less than 65 mA. For J-CDMA modulation, the module can deliver a 27.5-dBm output power (P_out), a 40% PAE, and a -50-dBc ACPR, while a 28-dBm P_out, a 42% PAE, and a -42-dBc ACLR are achieved for W-CDMA modulation.     

1.95GHz Doherty功率放大器设计

基于SMIC 0.18 μm RF CMOS工艺,设计了一款1.95 GHz的Doherty功率放大器.为了保持两路功放相位最大一致性,主功放(PA1)和辅功放(PA2)采用了同一种CMOS功率放大器,仅改变其偏压使其工作在不同模式.CMOS功率放大器为工作于AB类的两级放大电路,集成了输入和级间匹配网络;功分器以及λ...     

2.45 GHz高线性功率放大器设计

基于SMIC 0.18 μm RF-CMOS工艺,实现了一种工作于2.45 GHz的功率放大器,给出了电路仿真结果和电路版图.电路采用两级放大的结构,分别采用自偏置技术和电阻并联负反馈网络来缓解CMOS器件低击穿电压的限制,同时保证了稳定性的要求.为了提高线性度,采用一种集成的二极管线性化电路对有源器件的输入电容变化提供一种补偿机制,漏端的LC谐振网络和优化的栅偏置用来消除由跨导产生的非线性谐波.在3 V电源电压下,放大器功率增益为23 dB,输出1 dB压缩点约为25 dBm,对应的功率附加效率PAE可达35%.