A reconfigurable low-pass/high-pass \varDelta \varSigma ADC suited for a zero-IF/low-IF receiver

This paper presents the design of a reconfigurable delta sigma analog to digital converter. Its main degree of freedom is the choice of the noise shaping between low-pass and high-pass. Thanks to this reconfiguration parameter, the converter takes full advantage of both noise shapings and employs the most suited architecture depending on the received standard. Moreover, the low-pass/high-pass reconfiguration makes the analog-to-digital converter compliant for both the low-IF and the zero-IF receiver architectures. The paper also presents a novel reconfigurable dynamic element matching technique which efficiently addresses the digital to analog converter mismatch for both the high-pass and the low-pass delta sigma modulators. The sampling frequency and the quantizer number of bits are likewise adjustable. A GSM/UMTS compliant delta sigma analog to digital converter including reconfigurable decimator has been designed in a 1.2 V 65 nm CMOS process. The high-pass modulator is employed in a low-IF receiver for the GSM mode to profit from its robustness against offset and 1/f noise. For the UMTS mode, the low-pass modulator is employed in a zero-IF receiver because of its lower sensitivity to clock jitter.     

A low power reconfigurable multi-mode continuous time Delta Sigma modulator for seven different mobile standards with VCO-based quantizer

In this research a novel low power multi-mode continuous time Delta Sigma modulator was designed to be compatible with many mobile wireless standards. This modulator has a reconfigurable structure to adapt to various standards from 0.2 to 20 MHz. The designed modulator uses a VCO-based quantizer not only for lowering power consumption, but also for reducing the required chip area. The presented modulator can function with up to third order of noise shaping, or in a low power mode in which the loop filter is disabled and only the VCO-based quantizer is used. The proposed modulator was implemented and simulated in transistor level in 180 nm technology. This modulator can digitize at least seven standards (LTE (20 MHz)/WLAN/LTE (9 MHz)/WCDMA/UMTS/Bluetooth/GSM) with a favorable dynamic range (65–89 dB) and power consumption (9.1 mW–670 μW).     

Systematic top-down design of reconfigurable ΣΔ modulators for multi-standard transceivers

This paper addresses the design techniques of reconfigurable analog-to-digital converters for multi-standard wireless communication terminals. While most multi-standard converters reported so far follow an ad hoc design approach, which do not guarantee either efficient silicon area occupation or power efficiency in the different operation modes, the methodology presented here formulates a systematic design flow that ensures that both factors are considered at all hierarchical levels. Expandible cascade modulators are considered as the starting point to further reconfigurability at the architectural level. From here on, and using a combination of accurate behavioral modeling, statistical optimization techniques, and device-level simulation, the proposed methodology handles the design complexity of a reconfigurable converter while ensuring adaptive power consumption and boosting hardware sharing. A case study is presented where a reconfigurable modulator is designed to operate under three communication standards, GSM, Bluetooth, and UMTS, in a 130 nm-CMOS technology.     

Low-distortion bandpass /spl Sigma/-/spl Delta/ modulator for wireless radio receivers

A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM/GPRS standards.     

A triple-mode hexa-standard reconfigurable TI cross-coupled ΣΔ modulator

Hardware reconfigurability is an attractive solution for modern multi-standard wireless systems. This paper analyses the performance and implementation of an efficient triple-mode hexa-standard reconfigurable sigma-delta (∑?) modulator designed for six different wireless communication standards. Enhanced noise-shaping characteristics and increased digitisation rate, obtained by time-interleaved cross-coupling of ∑? paths, have been utilised for the modulator design. Power/hardware efficiency and the capability to acclimate the requirements of wide hexa-standard specifications are achieved by introducing an advanced noise-shaping structure, the dual-extended architecture. Simulation results of the proposed architecture using Hspice shows that the proposed modulator obtains a peak signal-to-noise ratio of 83.4/80.2/67.8/61.5/60.8/51.03 dB for hexa-standards, i.e. GSM????????/Bluetooth/GPS/WCDMA/WLAN/WiMAX standards with significantly less hardware and low operating frequency. The proposed architecture is implemented in 45 nm CMOS process using a 1 V supply and 0.7 V input range with a power consumption of 1.93 mW. Both architectural- and transistor-level simulation results prove the effectiveness and feasibility of this architecture to accomplish multi-standard cellular communication characteristics.     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

Time jitter in continuous-time /spl Sigma//spl Delta/ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order /spl Sigma//spl Delta/ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-/spl mu/m CMOS, the 0.55-mm/sup 2/ integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.     

Data Converter for Multistandard Mobile Phones

This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures. The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm². A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations.     

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-$muhbox m$CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8$hbox mm^2$and 0.7$hbox mm^2$die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth.     

A 3.3-mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18-/spl mu/m CMOS with 70-dB dynamic range in 2-MHz bandwidth

A quadrature fourth-order, continuous-time, /spl Sigma//spl Delta/ modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is -74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an I and Q /spl Sigma//spl Delta/ modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm/sup 2/ in a 0.18-/spl mu/m 1-poly 5-metal CMOS technology.     

Reconfigurable Multiband Antenna Designs for Wireless Communication Devices

New designs for compact reconfigurable antennas are introduced for mobile communication devices. The uniqueness of the antenna designs are that they allow various groups of their operating frequency bands to be selected electronically. In particular, each group of frequency bands, or mode, can be made to serve several different communication systems simultaneously. These systems may include various combinations of GSM, DCS, PCS, UMTS, Bluetooth, and wireless local-area network (LAN). Therefore, by electronically selecting different antenna modes, a variety of communication systems can be conveniently served by only one antenna. One advantage is that through the different operational modes, the total antenna volume can be reused, and therefore the overall antenna can be made compact. In these designs, the selection of the different modes is achieved by either i) switching different feeding locations of the antenna (switched feed) or ii) switching or breaking of the antenna's connection to the ground (switched ground). This paper demonstrates these two designs. For the first design of switched feed, it can support GSM, DCS, PCS, and UMTS. In the second design, the antenna makes use of a switched-ground technique, which can cover GSM, DCS, PCS, UMTS, Bluetooth, and 2.4 GHz wireless LAN. The designs are investigated when ideal switches and also various realistic active switches based on PIN diodes, GaAs field effect transistor, and MEMs configurations. The designs are verified through both numerical simulations and measurement of an experimental prototype. The results confirm good performance of the two multiband reconfigurable antenna designs.     

A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications

This paper describes the design and experimental characterization of a 0.13 μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.¹     

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as EDGE (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme, etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or to reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-operability. This paper presents analog and digital base-band circuits that are able to support GSM (with EDGE), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) level.     

A Testbed for Energy Profile Characterization of IP Services in Smartphones over Live Networks

Mobile phones are becoming pervasively used to access Internet and multimedia contents due to their increasing processing power and its wide range of featured wireless communication technologies (Infrared, Bluetooth, NFC, GSM, UMTS, HSPA, WiMax, LTE). In this paper we also introduce mobile devices as a pervasive testbed platform to characterize the energy consumption profile of Internet services. The most innovative advantage provided by our solution is the testbed’s flexibility and simplicity, making it possible to carry out extensive testing campaigns using actual mobile devices in live networks with real services.     

Transceiver Architecture Selection: Review, State-of-the-Art Survey and Case Study

Realizing multi-standard transceivers with maximum hardware reuse amongst the given standards is of great importance to minimize the manufacturing cost of emerging multi-defined service wireless terminals. A well architecture in conjunction with a reconfigurable building-block synthesis is essential to building formulate such a kind of tunable transceiver under a wide range of specifications. In this paper, we present both fundamental and state-of-the-art techniques that help selecting transceiver architecture for single-/multistandard design. We begin by reviewing the basic schemes and examining their suitability for use in modern wireless communication systems (GSM, WCDMA, IEEE 802.11, Bluetooth, ZigBee and Ultra Wideband). The justifications are confirmed with the state of-the-art choices through a survey (with 100+ references) of the most frequently used receiver and transmitter architectures reported in 1997 to 2005 IEEE solid-state circuit forums: ISSCC, CICC, VLSI and ESS-CIRC. State-of-the-art techniques for multistandability are analyzed through careful case studies of a cellular receiver for GSM/DCS/PCS/WCDMA, and several WPAN/WLAN transceivers for Bluetooth and IEEE 802.11a/b/g. They disclose, on the architecture and circuit levels, many ideas that have successfully inspired the recent development of wireless circuits and systems     

UMTS security: system architecture and hardware implementation

Universal mobile telecommunication system (UMTS) has specified security mechanisms with extra features compared to the security mechanisms of previous mobile communication systems (GSM, DECT). A hardware implementation of the UMTS security mechanism is presented in this paper. The proposed VLSI system supports the Authentication and Key Agreement procedure (AKA), the data confidentiality procedure, and the integrity protection procedure. The AKA procedure is based on RIJNDAEL Block Cipher. An efficient RIJNDAEL architecture is proposed in order to minimize the usage of hardware resources. The proposed implementation performs the AKA procedure within 76 µs comparing with the 500 ms that UMTS specifies. The data confidentiality and the integrity protection is based on KASUMI Block Cipher. The proposed KASUMI architecture reduces the hardware resources and power consumption. It uses feedback logic and positive‐negative edge‐triggered pipeline in order to make the critical path shorter, without increasing the execution latency. The S‐BOXes that are used from RIJNDAEL and KASUMI block ciphers have been implemented with combinational logic as well as with ROM blocks. Copyright © 2006 John Wiley & Sons, Ltd.     

Multimode $G_{m}$– $C$ Channel Selection Filter for Mobile Applications in 1-V Supply Voltage

A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18 mum CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.     

A highly digitized multimode receiver architecture for 3G mobiles

A highly digitized multimode receiver architecture is described. It is configured primarily for the Universal Mobile Telecommunication System (UMTS) and Global System for Mobile Communications (GSM) modes, but has the potential to operate in other modes such as cdma2000 as well. The receiver uses a single down conversion to mix the RF signal to a zero intermediate frequency (IF) for UMTS mode and a low IF for GSM. It uses a reconfigurable analog-to-digital converter (ADC) to digitize the IF signals as early as possible and to transfer most of the channel filtering into the digital domain. Only a minimum of automatic gain control (AGC) is employed. The architecture aims to maximize reuse of common hardware and to make significant gains in terms of design costs, size, and adaptability. System simulations confirm the feasibility and performance of the new concept.     

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.