The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in f/sub T/, f/sub max/, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Experimental demonstration and analysis of high performance and low 1/f noise Tri-gate MOSFETs by optimizing device structure

In this paper, we experimentally investigate the performance of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and the accumulation-mode (AM) FD-SOI MOSFETs. Firstly, we experimentally demonstrate that the drain current in AM multi-gate MOSFET is improved about 1.3 times compared with conventional inversion-mode (IM) MOSFETs with the same gate oxide. Secondly, we indicate that 1/f noise levels in AM MUGFETs are obviously suppressed compared with the conventional IM MUGFETs. The advantages resulted from the AM device structure for MUGFETs are demonstrated in this experiment.     

High-power-density 4H-SiC RF MOSFETs

The authors have made the first 4H-SiC RF power MOSFETs with cutoff frequency up to 12 GHz, delivering RF power of 1.9 W/mm at 3 GHz. The transistors withstand 200 V drain voltage, are normally off, and show no gate lag, which is often encountered in SiC MESFETs. The measured devices have a single drain finger and a double gate finger, and a total gate width of 0.8 mm. To their knowledge, this is the first time that power densities above 1 W/mm at 3 GHz are reported for SiC MOSFETs.     

Modeling the partition of noise from the gate-tunneling current in MOSFETs

Expressions for the spectral densities of the gate/source and gate/drain noise currents caused by current flow through the gate oxide of MOSFETs are derived. It is shown that these noise currents can also be expressed in terms of equivalent gate and drain noise currents, and by linearizing the position dependence of the gate current density, simple analytic expressions for these equivalent noise currents and their correlation are obtained in terms of the total gate current and the drain/source partition ratio. It is also shown that the predictions of this simple theory are consistent with published experimental data and results from numerical simulations.     

Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs

An extensive characterization of the on-state breakdown characteristics of GaAs based MESFETs and HEMTs has been carried out by means of DC and pulsed measurements and of circuit simulations. A computer-controlled, three-terminal Transmission Line Pulse (TLP) system with 50-100 ns pulse width and sub-ns risetime has been developed, which allows automated pulsed measurements of device I-V characteristics. The TLP system has been adopted for nondestructive measurements of the on-state breakdown characteristics of GaAs MESFETs and HEMTs up to unprecedented values of gate current density (I/sub G//W=30 mA/mm has been reached), in strong avalanche conditions. The device behavior in strong avalanche conditions is dominated by a parasitic bipolar effect (PBE) similarly to SOI and bulk Si MOSFETs. By taking into account this and other parasitic effects, an equivalent circuit model, suitable for SPICE simulations has been developed. The proposed model is capable of predicting the exact behavior of the gate and drain currents in both weak and strong avalanche conditions.     

Comparison between the effects of positive noncatastrophic HBM ESDstress in n-channel and p-channel power MOSFETs

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

超薄栅n-MOSFETs热载流子寿命预测模型

对氧化层厚度为 4和 5 nm的 n- MOSFETs进行了沟道热载流子应力加速寿命实验 ,研究了饱和漏电流在热载流子应力下的退化 .在饱和漏电流退化特性的基础上提出了电子流量模型 ,此模型适用于氧化层厚度为 4— 5 nm或更薄的器件     

Investigation of the impact of Al mole-fraction on the consequences of RF stress on Al/sub x/Ga/sub 1-x/N/GaN MODFETs

Variations of the low-frequency noise (LFN), power, and dc characteristics of a variety of SiN/sub x/ passivated AlGaN/GaN MODFETs with different values of Al mole-fraction, gate length, and gate drain spacing upon RF stress are investigated. It is experimentally evidenced that the variation of Al mole-fraction (x) of the barrier Al/sub x/Ga/sub 1-x/N layer from 0.2 to 0.4, has no considerable impact on the drain and gate low-frequency noise current characteristics. The most noticeable variation on the device characteristics upon long-term RF stressing has been on the pinch-off voltage. Although no material degradation by increasing the Al mole-fraction has been evidenced through the low-frequency noise data, it is observed that the variation of pinch-off voltage upon RF stressing becomes more important as the Al mole-fraction increases.     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

Off-state gate current in n-channel MOSFETs with nitrided oxidegate dielectrics

The authors report on the off-state gate current (I_g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I_g at drain voltages as low as 4 V and an I_g injection efficiency reaching 0.8, as compared to 8.5 V and 10^-7 in SiO₂ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I_g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure     

Gate current in OFF-state MOSFET

The source of the gate current in MOSFETs due to an applied drain voltage with the gate grounded is studied. It is found that for 100-Å or thinner oxide, the gate current is due to Fowler-Nordheim (F-N) tunneling electrons from the gate. With increasing oxide thickness, hot-hole injection becomes the dominant contribution to the gate current. This gate current can cause I_D walkout, which is a decrease in the gate-induced drain leakage current, and hole trapping, which becomes important for device degradation study. It can also be used to advantage in EPROM (erasable programmable read-only memory) erasure     

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

1.5-nm gate oxide CMOS on [110] surface-oriented Si substrate

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.     

A method to extract mobility degradation and total seriesresistance of fully-depleted SOI MOSFETs

Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed     

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs

Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain–current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications.      

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

Low noise RF MOSFETs on flexible plastic substrates

We report a low minimum noise figure (NF/sub min/) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-/spl mu/m RF MOSFETs, after thinning down the Si substrate to 30 /spl mu/m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NF/sub min/ to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-/spl mu/m node (L/sub g/=80 nm) devices.     

Ultrathin gate oxide CMOS with nondoped selective epitaxial Sichannel layer

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO₂-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated