Two-dimensional subthreshold analysis of sub-micron GaN MESFET

An analytical two-dimensional (2D) model to accurately predict the channel potential and electric field distribution in sub-micron GaN MESFET operating in the sub-threshold regime based on (2D) analytical solution of Poisson's equation using superposition principle is presented. The results so obtained for channel potential, electric field, threshold voltage, etc are compared with simulated data using ATLAS 2D device simulator. The model is then extended to predict the current voltage characteristics and the effects of drain induced barrier lowering (DIBL) on the performance. Furthermore, the sub-threshold output characteristics of the device are also interpreted qualitatively.     

Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN HEMT for enhanced carrier transport efficiency

The present work explores the features of gate material engineered (GME) AlGaN/GaN high electron mobility transistor (HEMT) for enhanced carrier transport efficiency (CTE) and suppressed short channel effects (SCEs) using 2-D sub-threshold analysis and device simulation. The model accurately predicts the channel potential, electric field and sub-threshold current for the conventional and GME HEMT, taking into account the effect of work function difference of the two metal gates. This is verified by comparing the model results with the ATLAS simulation results. Further, simulation study has been extended to reflect the wide range of benefits exhibited by GME HEMT for its on-state and analog performance. The simulation results demonstrate that the GME HEMT exhibits much higher on current, lower conductance and higher transconductance as compared to the conventional HEMT due to improved CTE and reduced SCEs. This in turn has a direct bearing on the device figure of merits (FOMs) such as intrinsic gain, device efficiency and early voltage. Tuning of GME HEMT in terms of the relative lengths of the two metal gates, their work function difference and barrier layer thickness has further been carried out to enhance the drive current, transconductance and the device FOMs illustrating the superior performance of GME HEMT for future high-performance high-speed switching, digital and analog applications.     

IGFET Analysis through numerical solution of Poisson's equation

Numerical techniques have been used to obtain the field distribution in IGFETs under saturated bias conditions. The numerical solution of Poisson's equation is obtained with fewer simplifying assumptions than are necessary to obtain an analytic solution. The numerical solution is used to calculate the change in channel length as bias values are varied. These changes are used to predict the voltage dependences of drain current, drain conductance and transconductance in saturation. The potential solutions also permit a rough calculation of breakdown voltages. A comparison is made between the theoretical results and measurements on IGFETs of varying dimensions and doping concentrations.     

Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field

In this paper a two dimensional analytical model of channel potential and electric field for an asymmetric and symmetric double gate three-terminal (3T) and four-terminal (4T) silicon n-tunnel field effect transistor (Si-nTFET) device in sub-threshold region, without surface accumulation or inversion, is presented. Since the modeling has been done in subthreshlod regime operation, no Quantum Mechanical (QM) study has been taken. A very good agreement of analytically modeled results with the TCAD simulated results for the three-terminal (3T) and four-terminal (4T) Si-nTFET device was found. The model presented is based on the physics of the device. The modeling is for a 3T/4T asymmetric Tunnel FET and with appropriate changes in the device parameters we can also model for symmetric devices as well. The modeling scheme is thus quite robust.     

杂质吸附对背栅MoS2场效应晶体管电学性能的影响

为了探究MoS2（二硫化钼）薄膜吸附的杂质分子对载流子输运以及相关器件的电学性能造成的影响,制备了多层MoS2背栅场效应晶体管。实验结果表明：当MoS2器件的沟道暴露在空气中时,在不同的偏压条件和扫描条件下,器件表现出不同的回滞窗口和不同的亚阈值斜率。因此,只有减小了外界吸附分子的影响,才能获得具有稳定电学性能的MoS2器件,并确保迁移率、亚阈值斜率、开启电压等重要电学参数的可靠性。     

沟道应力对纳米尺度MOSFET器件特性的影响

利用ISE DESSIS器件模拟工具，模拟了纳米尺度的MOSFETs器件沟道中存在应力时的器件特性，分析了应力大小和方向发生变化对MOSFET的阈值电压、亚阈特性等器件特性的影响.     

Extraction method for polycrystalline TFT above and below threshold model parameters

A procedure is presented to extract above and sub-threshold model parameters in polysilicon TFTs. It is based on the integration of the experimental data current, which has the advantage of reducing the effects of experimental noise. This method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold and sub-threshold parameters. We already presented a unified extraction method for the above threshold parameters of a-Si:H and polysilicon TFTs, where the above-threshold regime the mobility is modeled as a function of the gate voltage to a power. An integration procedure is used to extract the device model parameters. In this paper, we complete the extraction procedure to cover all the device operation regions, that is the sub-threshold and above-threshold regimes. The extraction procedure provides in addition the possibility of monitoring the crystallization process of a-Si:H TFTs into polysilicon, which has become a widely used process of fabricating low temperature polysilicon TFTs. The process of polycrystallization manifests itself by a variation and change in sign of one of the model parameters. Extracted parameters can be correlated to input parameters required by AIM-Spice circuit simulator for device modeling. The accuracy of the simulated curves using the extracted parameters is verified with measurements.     

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.     

A 2D Transconductance and Sub-threshold behavior model for triple material surrounding gate (TMSG) MOSFETs

A 2D analytical model for transconductance, Sub-threshold current and Sub-threshold swing for Triple Material Surrounding Gate MOSFET (TMSG) is presented in this paper. Based on the solution of two dimensional Poisson equation, the physics based model of sub-threshold current of the device is derived. The model also includes the effect of gate oxide thickness and silicon thickness on the sub-threshold swing characteristics. Transconductance to drain current ratio of the triple material surrounding gate is calculated since it is a better criterion to access the performance of the device. The effectiveness of TMSG design was scrutinized by comparing with other triple material and dual material gate structures. Moreover the effect of technology parameter variations is also studied and proposed. This proposed model offers basic guidance for design of TMSG MOSFETs. The results of the analytical model are compared with the MEDICI simulation results thus providing validity of the proposed model.     

浮栅器件栅耦合系数修正的探讨

提取浮栅器件栅耦合率的方法一般都是针对不可忽略的沟道耦合现象进行修正.对这些方法进行了比较、分析发现,对于短沟道浮栅器件,会由于参考器件存在明显的DIBL/SIBL效应,使提取的源、漏耦合系数偏大产生了很大的误差.提出了一种对亚阈值斜率法提取浮栅器件栅耦合系数的修正方法,结合了DIBL/SIBL效应因子,基于亚阈值斜率之比来较简单地实现更精确的近似,得到的栅耦合系数与设计值吻合较好,误差在2%以内,表明此修正法是合理且精确的.     

Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range

This paper presents two dimensional temperature dependent analytical model of Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data using ATLAS 3D device simulator for wide operating temperature i.e. 300–500 K for channel length down to 32 nm technology node. In this work, a temperature dependent analytical expression of drain current for sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reduced leakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverter performance and hence ISESON can be widely used in CCD camera as well as for fast switching applications. Further, we have also investigated the impact of temperature on electrical characteristics of ISESON MOSFET which are important for analog applications.     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

非对称HALO-LDD掺杂石墨烯纳米条带场效应管的电学特性研究(英文)

随着器件沟道尺寸的不断缩小,短沟道效应(SCE)和漏致势垒降低效应(DIBL)对常规类MOSFET结构的石墨烯纳米条带场效应管(GNRFET)影响变大,从而引起器件性能下降。文中提出了一种新型采用非对称HALO-LDD掺杂结构的GNRFET,其能够有效抑制器件中SCE和DIBL,改善器件性能。并采用一种量子力学模型研究GNRFET的电学特性,该模型基于二维NEGF(非平衡格林函数)方程和Poisson方程自洽全量子数值解。结合器件的工作原理,研究了GNRFET的电学特性和器件结构尺寸效应,通过与采用其他掺杂结构的GNRFET的电学特性对比分析,发现这种掺杂结构的石墨烯纳米条带场效应管具有更低的泄漏电流、更低的亚阈值斜率和DIBL以     

FINFET的三维模拟

采用三维模拟软件对具有FINFET结构的SOI-MOSFET进行了模拟.研究了FINFET的I-V特性、亚阈值特性、短沟道效应等.模拟发现,通过降低fin的高度可以有效地抑制短沟道效应与提高器件的性能,因此fin的高度是器件设计中一个关键参数.模拟结果表明FINFET在特性上优于传统的单栅器件.     

IGFET hot electron emission model

A new model for hot electron emission into the oxide layer of IGFETs is presented. When IGFETs operate under high gate and drain bias conditions, electrons are accelerated by the high drain field and injected into the oxide layer at a certain probability. The present model takes into account the following: (1) the energy dependence of hot electron scattering probability, (2) the three-dimensional angle at which electrons are injected into the oxide layer, (3) the quantum effect at the SiSiO₂ interface that gives the reflection probability, and (4) the scattering and reaching probabilities without energy loss. The total emission current is obtained by a five-fold integral over the energy, position and solid angle elements. The current thus predicted is expected to be two or three orders of magnitude smaller than that from Phillips' model previously proposed for IGFET emission current and hence closer to experimintal data. The present model can give the position dependence of emitted current and is suitable for incorporation into two-dimensional numerical analysis.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si),gallium arsenide (GaAs),alminium gallium arsenide (AlxGa1xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator.The proposed devices are compared on the basis of inverse subthreshold slope (SS),ION/IoFF current ratio and leakage current.Using Si as the channel material limits the property to reduce leakage current with scaling of channel,whereas the AlxGalxAs based DG tunnel FET provides a better ION/IoFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits.The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down.The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time,which makes it suitable for memory based circuits.     

硅膜厚度对0.1μm SOI槽栅NMOS器件特性的影响

SOI技术和槽栅MOS新器件结构是在改善器件特性方面的两大突破,SOI槽栅MOS器件结构能够弥补体硅槽栅MOS器件在驱动能力和亚阈值特性方面的不足,同时也保证了在深亚微米领域的抑制短沟道效应和抗热载流子效应的能力.仿真结果显示硅膜厚度对SOI槽栅MOS器件的阈值电压、亚阈值特性和饱和驱动能力都有较大影响,选择最佳的硅膜厚度是获得较好的器件特性的重要因素.     

50nm SOI-DTMOS器件的性能

利用二维器件模拟软件ISE对5 0nm沟道长度下SOI DTMOS器件性能进行了研究,并与常规结构的SOI器件作了比较.结果表明,在5 0nm沟长下,SOI DTMOS器件性能远远优于常规SOI器件.SOI DTMOS器件具有更好的亚阈值特性,其亚阈值泄漏电流比常规SOI器件小2～3个数量级,从而使其具有更低的静态功耗.同时,SOI DTMOS器件较高的驱动电流保证了管子的工作速度,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应,从而保证了在尺寸进一步减小的情况下管子的性能.对SOI DTMOS器件的物理机制进行了初步分析,揭示了其性能远优于常规结构的物理本质