A simple model for scaled MOS transistors that includes field-dependent mobility

A simple MOS model that is suitable for hand calculations, but which includes the effect of normal and tangential electric fields on carrier mobility, is described. This device model is derived from semiphysical models for the field dependence of carrier mobility to accurately predict the effect of reduced dimensions. Fitting parameters for n-channel transistors were extracted. The model is used to examine the effect of reduced mobility at high electric fields on logic switching speed and device transconductance.     

A simple model for computer simulation of Schottky-barrier diodes

To simulate the electrical characteristics of metal-semiconductor Schottky barrier diodes, a numerical analysis program based on the Shockley's semiconductor equations has been established. The thermionic emissions of electrons and holes from semiconductor to metal as well as the electric field in the interfacial layer are taken as the derivative boundary conditions of the nonlinear equations. The forward and reverse current-voltage characteristics of various metal-silicon and metal-silicide-silicon Schottky barrier diodes can be simulated by properly choosing the zero-field barrier height and the interfacial-layer capacitance. The barrier height variation as a function of applied voltage is related to the space-charge density and the interfacial-layer capacitance. The nonideality of forward characteristics is attributed to the bending of majority carrier imref and the raising of barrier height. The soft behavior of reverse characteristics can be modeled in terms of the interfacial-layer capacitance.     

Comparison of modulation doped effect in negative differential resistance field effect transistors (NDRFETs)

N-shaped negative differential resistance field effect transistors (NDRFETs) have been fabricated and demonstrated. The interesting N-shaped NDRs are three terminal controlled phenomena. This N-shaped NDR behavior is found in the higher drain-to-source voltage (V_DS) regime and is obtained both at positive and negative gate-to-source bias (V_GS). We believe that the NDR phenomena are attributed to the real space transfer (RST) effect. Due to the modulation doped effect and different barrier height, the NDR behavior can easily be controlled. The influence of V_GS bias on the NDR characteristics is also investigated.     

A process for high yield and high performance carbon nanotube field effect transistors

Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139 mV/dec, high transconductance of 1.27 μS, and high I_on/I_off ratio of 10⁶ can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future.     

Optimizing the fabrication process for high performance graphene field effect transistors

As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N₂ ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (～500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm²/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10^?6 Ω cm² to 8.8 × 10^?6 Ω cm², which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at V_D = 0.5 V, which is the highest value among CVD graphene FETs published to date.     

Impact of injection limitations on the contact resistance and the carrier mobility of organic field effect transistors

The contact resistance as well as the mobility have developed to key performance indicators for benchmarking organic field-effect transistors. Typically, conventional methods for silicon transistors are employed for their extraction thereby ignoring the peculiarities of organic transistors. This work outlines the required conditions for using conventional extraction techniques for the contact resistance and the mobility based on TCAD simulations and experimental data. Our experimental data contain both staggered and coplanar structures fabricated by exploiting different optimization techniques like SAM treated electrodes, different shearing speeds, PS blending and silicon oxide functionalization. In addition, the work clarifies how injection limited current–voltage characteristics can affect high-performance organic field-effect transistors. Finally, we introduce a semi-physical model for the contact resistance to accurately interpret extracted benchmark parameters by means of the transfer length method (TLM). Guidelines to use conventional extraction techniques with special emphasis on TLM are also provided.     

C60场效应晶体管的制备及修饰层对器件性能影响的研究

以重掺杂Si片作为衬底,SiOe／聚甲基丙烯酸甲酯（PMMA）为双栅绝缘层,C60为有源层,制备了不同修饰层的有机场效应晶体管（OFETs）;研究了不同修饰层的器件对于场效应性能的影响。实验表明,与未加修饰层的器件相比,经过修饰的器件性能有一定的提高,其中Alqa／LiF双修饰层器件的场效应迁移率达到最大,为1．6×1...     

Titanium silicide/germanide formation on submicron features for high mobility SiGe channel field effect transistors

The formation of self-aligned Ti(Si_(1−x)Ge_(x))₂ on submicron lines is described. The silicide/germanide is formed by reacting sputtered Ti with epitaxially grown Si_(1−x)Ge_(x) of composition and thickness relevant to high mobility Si_(1−x)Ge_(x) channel field effect transistors. Ti(Si_(1−x)Ge_(x))₂ formation on narrow lines was carried out on phosphorous doped material, because of the well known difficulties of forming silicide on heavily n-doped silicon. A companion set of boron doped blanket films was also processed. The results show that the process temperature required for the minimization of silicide/germanide sheet resistance is reduced as compared to silicide formation on Si alone. However, the silicide/germanide films agglomerate with increased high temperature processing more easily than pure silicide. The thermal stability is degraded more for films with higher Ge content and is a strong function of dopant type. Silicide/germanide formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 10% have a line width dependence similar to silicide formation. Formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 27% display an inverse line width dependence, with higher overall sheet resistance. Formation of silicide/germanide on blanket films of boron doped Si_(1−x)Ge_(x) with x = 27% behaved similar to the formation of silicide on silicon.     

Interface dipole: Effects on threshold voltage and mobility for both amorphous and poly-crystalline organic field effect transistors

We report a detailed comparison on the role of a self-assembled monolayer (SAM) of dipolar molecules on the threshold voltage and charge carrier mobility of organic field-effect transistor (OFET) made of both amorphous and polycrystalline organic semiconductors. We show that the same relationship between the threshold voltage and the dipole-induced charges in the SAM holds when both types of devices are fabricated on strictly identical base substrates. Charge carrier mobilities, almost constant for amorphous OFET, are not affected by the dipole in the SAMs, while for polycrystalline OFET (pentacene) the large variation of charge carrier mobilities is related to change in the organic film structure (mostly grain size).     

Low field mobility, effective saturation velocity and performance of submicron GaAs MESFETs

An analytical model is proposed which relates the transconductance of submicron GaAs MESFETs to a low field mobility, effective electron saturation velocity and device geometry and doping. The model predicts that the effective saturation velocity determines the performance of the devices at relatively high pinch-off voltages (Vpo > 5 V). At smaller pinch-off voltages (especially for enhancement-mode devices) the low field mobility becomes increasingly important, leading to additional advantages of GaAs devices over Si devices. Another prediction is a higher transconductance in thinner and higher-doped devices. This effect is also more important for devices with low pinch-off voltages. The obtained results may be used to deduce the effective values of the electron drift velocity in GaAs MESFETs as a function of the gate length.     

Morphology optimization for achieving air stable and high performance organic field effect transistors

To develop an all organic active matrix light emitting display required for large area thin display, electronic paper and electronic paints, Si-based thin film transistor has to be replaced with organic thin film transistor (OTFT). The most important issues in OTFT are the low charge carrier mobility and poor stability under ambient conditions, which critically depend on how organic thin films are grown on different substrates. Here we show that both these issues are correlated and can be overcome by certain surface morphology which can only be achieved through anisotropic growth. Careful control of different growth parameters can lead to unprecedented control on thin film morphology which has been shown to be engineered reversibly and reproducibly. High temperature and low evaporation rate increase the diffusive mobility of molecules, which are responsible for the stacking of molecules to higher length scales. By carefully choosing a temperature and evaporation rate, elongated rod-like grains were grown for achieving high performance and stable thin film transistors.     

Gate current model for the hot-electron regime of operation inheterostructure field effect transistors

A model to describe the dependence of the gate current with source-to-drain voltage was developed and used to predict the performance of AlGaAs/InGaAs/GaAs HFETs. Our model describes the charge injection transistor (CHINT) regime of operation and account for real-space electron transport. In this model, the saturation of the hot-electron gate current is explained by the rapid drop in the energy relaxation time caused by the real-space transfer of electrons. Good correlation between the experimental and theoretical data was found for temperatures ranging from 198 to 398 K. Our experimental and theoretical results should be accounted for in the design of HFET devices and integrated circuits     

On the validity of the gradual channel approximation for junction field effect transistors with drift velocity saturation

The errors are analyzed which result from the gradual channel approximation for junction field effect transistors with drift velocity saturation of carriers. Near the drain the neglect of the second derivative of potential with respect to position coordinate along the channel in Poisson's equation for the depletion layer is found to be more stringent than that of the field component normal to the channel boundary. The resulting errors are presented as a function of a dimensionless parameter which is proportional to mobility and pinch-off voltage and inversely proportional to channel length and saturation drift velocity. A modified channel boundary is constructed at which the boundary condition is exactly satisfied.     

A new method for temperature mapping on GaAs field effect transistors

In this paper, a method is described, how to apply the technique of spatially resolved photoluminescence (PL) spectroscopy for the measurement of the local channel temperature in GaAs-based field effect transistors. This spectroscopic technique uses a focused laser beam which scans directly the surface of a chip inside its package. The temperature is deduced from the corresponding wavelength shift of the PL peak. In the case of a typical heterostructure-based transistor (like the pseudomorphic high electron mobility transistors studied here) a spatial resolution of 1 pm and a temperature resolution of °C is demonstrated.     

Effects of P3HT concentration on the performance of organic field effect transistors

Top-contact organic field effect transistors(OFETs) based on poly(3-hexylthiophene)(P3HT) with different concentrations in chloroform(CHCl3) are fabricated.The output characteristics indicate that the P3HT concentration has significant influence on the OFET devices.The performance of the devices firstly is enhanced with increasing the P3HT concentration,and then decreases.The optimized devices with the P3HT concentration of 2 mg/mL show the best performance.The fieldeffect mobility is up to 1.4×10-2 cm2/Vs,...     

A model for the critical voltage for electrical degradation of GaN high electron mobility transistors

It has recently been postulated that GaN high electron mobility transistors under high voltage stress degrade as a result of defect formation induced by excessive mechanical stress that is introduced through the inverse piezoelectric effect. This mechanism is characterized by a critical voltage beyond which irreversible degradation takes place. In order to improve the electrical reliability of GaN HEMTs, it is important to understand and model this degradation process. In this paper, we formulate a first-order model for mechanical stress and elastic energy induced by the inverse piezoelectric effect in GaN HEMTs which allows the computation of the critical voltage for degradation in these devices.     

High-resolution direct-writing of metallic electrodes on flexible substrates for high performance organic field effect transistors

We report on organic field-effect transistors (OFETs) with sub-micrometer channels fabricated on plastic substrates with fully direct-written electrical contacts. In order to pattern source and drain electrodes with high resolution and reliability, we adopted a combination of two digital, direct writing techniques: ink-jet printing and femtosecond laser ablation. First silver lines are deposited by inkjet printing and sintered at low temperature and then sub-micrometer channels are produced by highly selective femtosecond laser ablation, strongly improving the lateral patterning resolution achievable with inkjet printing only. These direct-written electrodes are adopted in top gate OFETs, based on high-mobility holes and electrons transporting semiconductors, with field-effect mobilities up to 0.2 cm²/V s. Arrays of tens of devices have been fabricated with high process yield and good uniformity, demonstrating the robustness of the proposed direct-writing approach for the patterning of downscaled electrodes for high performance OFETs, compatibly with cost-effective manufacturing of large-area circuits.     

Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs

The substrate bias and operating temperature effects on the performance of erbium-silicided Schottky-barrier SOI nMOSFETs have been studied. The temperature dependence of the threshold voltage, the current ratio of I_ON/I_MIN, and the subthreshold swing has been investigated. From temperature dependence of the drain current, it is confirmed that the carrier transport mechanism changes from thermionic emission and tunneling at low gate voltage to drift-diffusion at the high gate voltage. By applying substrate bias voltage, the I_ON/I_MIN ratio and subthreshold swing can be improved. By investigating the substrate bias dependence of I_ON/I_MIN ratio, subthreshold swing, and DIBL, the optimum substrate bias voltage is suggested.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.