Electrical and structural effects on ionizing radiation in IGFETS

In terms of initial device yield, and long term reliability, process induced radiation damage represents an area of considerable concern. The processes that need to be examined include Ion Implantation, X-ray, E-Beam and Ion Beam lithography, Electron Beam metal evaporation, Sputtering, Reactive Ion Etching, and even SEM examination. The paper discusses the effects of synchrotron X-radiation in the energy range 300-100 eV, as well as Al Ka exposures which simulate the effective wavelength of storage rings planned for X-ray lithography. It will describe such effects in the context of preliminary studies dealing with varying rad exposure level at constant gate insulator thickness, as well as the behavior at several rad exposure levels as a function of gate insulator thickness. Data will be presented indicating that despite prevailing beliefs, damage in the synchrotron range follows a linear relationship over the thickness range from less than 10 nm to 50 nm, indicating strongly that damage resides near the interface and is constant with increasing insulator thickness. It will be shown that such behavior is consistent with a simple model. Even if such damage can be annealed completely using normal techniques, which is questionable, there are wide-ranging implications concerning the rad hardness of scaled devices.     

The effects of fixed bulk charge on the characteristics of metal-oxide-semiconductor transistors

The theory of the characteristics of the MOS transistors is developed based on a model in which both the bulk charge due to the ionized impurity in the semiconductor substrate and the difference between the electrostatic potential and the voltage drop in the channel are included. A detailed comparison of the theory is made with experimental data of gate capacitance, drain current voltage characteristics, and transconductance characteristics on both N-channel and P-channel silicon devices with thin (2000 A) and thick (6200 and 8400 A) oxides under the gate electrode. The correlation is good using the surface mobility as the adjustable parameter. Mobility reduction in the saturation transconductance characteristics is predicted in the theory and demonstrated in the experimental data. It arises entirely from the bulk charge, which modifies the device characteristics, and is not associated with some basic surface scattering phenomena, which further reduce the mobility. It is also demonstrated experimentally that to evaluate a physically meaningful surface mobility from the conductance of the channel, the interface surface state charge Qsscannot be assumed constant in the devices used in this study.     

Output characteristics of short-channel field-effect transistors

A recent model for hot-electron MOS transistors [4], [5] is generalized for short-channel field-effect transistors. It is based on six to seven parameters for the carrier mobility under the influence of transverse and Iongitudinal electric fields, for the threshold voltage and its dependence on drain bias, and for a finite longitudinal field at pinch-off. Such important features of short-channel FET's like reduced available current and voltage gain are well represented, where the latter turns up as important limiting factor in submicron devices. Effects of zero-field mobility, impurities, and device geometry are stated explicitly. The results are confirmed by measured data on 0.9-µm silicon gate MOSFET's.     

Theoretical considerations on the effects of bulk charge on VMOST characteristics

A linear approximation to the bulk-charge effect in short-channel VMOS devices is presented which allows for an explicit solution to the volt-ampere characteristics in the presence of velocity saturation effects. The results are shown to agree closely with the more complex exact analysis.     

Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10^-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.     

Device characteristics of short-channel and narrow-width MOSFET's

MOS devices have become smaller and smaller as the integrated circuit technology advances. A thorough understanding of the device characteristics of these small-size devices is important. In this paper, three small-geometry effects; namely, short-channel effect (SCE), narrow-width effect (NWE), and minimum-size effect (MSE) (which combines SCE and NWE together) are discussed. The variations of threshold voltage, mobility, and drain current are illustrated for minimum-size devices. The threshold voltage decreases as channel length decreases but increases as device width decreases. Carrier mobility also decreases as the device size becomes small. Simple device models of minimum-size devices are proposed for threshold voltage and carrier mobility. Experimental results of threshold voltage, mobility, and drain current are compared with the calculated results.     

Piezoresistive characteristics of short-channel MOSFETs on (100)silicon

This paper demonstrates that the intrinsic piezoresistive response of the MOSFET channel is independent of length. The reported fall-off of the piezoresistive response of the transistor in short channel devices is shown to be the result of parasitic series resistance in the source of the transistor. At the same time, the experimental results demonstrate that the threshold voltage of the devices is essentially independent of stress. The results are verified for three independent processes     

An analytical model for the above-threshold characteristics ofpolysilicon thin-film transistors

An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E_c -0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with experimental data of plasma-passivated and unpassivated TFT devices in a wide range of gate and drain biases and temperature. The correlation of transconductance to gate bias is also investigated. It is found that the decrease of grain-boundary barrier potential with gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes a decrease of transconductance at high gate bias     

Surface state charge effects on very low current transistor characteristics

The carrier transport characteristics of a low current transistor were measured. The effect of the total surface state charge Qsson the 1kT and 2kT components of Iband Icwas determined.     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices     

Effect of comparator offset on the linearity of charge sharing ADCs

The charge-sharing (CS) switching scheme appeared recently as an alternative to the charge-redistribution (CR) ADC for moderate-resolution low-power applications. One advantage of the CS is that it requires less demanding reference and input buffers. On the other hand, the CS ADC is very sensitive to the comparator offset, because the latter is translated into non-linearity on the ADC transfer curve. This paper examines the mechanism that causes this non-linearity and proposes a closed-form expression for the maximum effective resolution that a CS ADC may achieve in the presence of comparator offset. Finally, the model is verified with behavioral simulations.     

The voltage-doping transformation: a new approach to the modelingof MOSFET short-channel effects

It is shown that the influence of the drain-source field on the potential barrier height is physically equivalent to and can be replaced by a reduction in channel doping concentration according to a formula derived from the two-dimensional Poisson equation. The actual barrier height for any drain bias and channel length, on which the derived equation depends, can be calculated easily using well-known one-dimensional (long-channel) solutions. This simple but general procedure, called the voltage-doping transformation (VDT), is shown to lead to analytically calculated potential distributions in fairly good agreement with two-dimensional numerical simulation. An application of the VDT to threshold voltage (V_tj) calculations also is shown. The V_th model is compared with measurements taken on implanted n-MOSFETs with various channel lengths. Good agreement demonstrates the accuracy of both the VDT and the new V_th model     

A simplified model of short-channel MOSFET characteristics in the breakdown mode

When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.     

The improvement of short-channel effects due to oxidation-inducedboron redistribution for counter-implantation p-MOSFET's

Delayed appearance of short-channel effects in the threshold voltage falloff has been observed for counterimplantation p-MOSFETs. The phenomenon is attributed to the oxidation-induced boron redistribution along the channel. SUPREM-3 and MINIMOS-5 and the Orlowski method were used to quantitatively characterize this behavior. Quite good agreement between simulation and experimental data were obtained. It was found that the device characteristics of submicrometer counterimplanted p-MOSFETs are improved due to the effects of boron redistribution near the channel edge     

An analytical two-dimensional simulation for the GaAs MESFETdrain-induced barrier lowering: a short-channel effect

An analytic model for simulating the GaAs MESFET drain-induced barrier lowering and its effect on device performance are discussed. The potential barrier between the source and drain of a field-effect transistor in or near the subthreshold region is lowered by increasing the drain voltage. As the barrier is lowered to be comparable to the thermal energy, an appreciable current will flow through the channel, and the device will begin to conduct. This effect causes the threshold-voltage-control problem and degrades the device performance     

Effects of source/drain implants on short-channel MOSFET I-V andC-V characteristics

The effects of source/drain implants on n-channel MOSFET I-V and C-V characteristics are measured and compared for the lightly doped drain (LDD) and the large-angle-tilt implanted drain (LATID) devices. We show that despite substantial improvement in hot-carrier reliability for LATID devices, the LATID design might have a limited range of application for short-channel MOSFETs. This is because as a result of enhanced V_TH roll-off and increased overlap capacitance for the LATID devices compared to LDD devices, the device/circuit performance degrades. The degradation of performance becomes more pronounced as device length is reduced. These results are confirmed by both experimental data and 2-dimensional numerical simulations     

Thermal effects on the characteristics of AlGaAs/GaAsheterojunction bipolar transistors using two-dimensional numericalsimulation

Two-dimensional numerical simulations incorporating the spatial distributions of the energy band and temperature were used to study AlGaAs/GaAs heterojunction bipolar transistor characteristics. It was found that the negative differential resistance and the reduction of the base-emitter voltage for a constant base current in the active region are due to thermal effects. The differential current gain and cutoff frequency decrease when the transistor is operated at high power levels. The temperature distribution of the transistor operated in the active region shows a maximum at the collector region right beneath the emitter mesa. When the transistor is operated in the saturation region, the emitter contact region may be at a slightly lower temperature than the heat sink temperature. This thermoelectric cooling effect results from the utilization of the thermodynamically compatible current and energy flow formulations in which the energy band discontinuities are part of the thermoelectric power     

Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness

A systematic study of the dependence of short-channel effects (SCEs) on the channel thickness (Tch) of double-gate MOSFETs revealed that there is a particular range of Tch in which SCEs are significantly degraded compared to those of conventional planar MOSFETs. This phenomenon was found to originate from the electric field penetrating the channel region from the drain due to the disappearance of a neutral region in the channel. This dependence of this phenomenon on device parameters such as the channel doping concentration (Nc), the equivalent oxide thickness (EOT) and the gate length (Lg) was examined. The degradation of SCEs due to an inappropriate Tch was found to become more significant as Nc and Lg are reduced.     

Influence of short-channel effects on dopant profiles obtained from the DC MOSFET profile method

Distortions in the dopant density profile obtained from dc MOSFET measurements due to short-channel effects are not properly predicted by present two-dimensional charge sharing, or charge conservation, models. The comparison of dopant profile data with predictions based on charge conservation models is a powerful technique for evaluating the accuracy of these models.     

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs

In this paper, a fundamental investigation on short-channel effects (SCEs) in 4H-SiC MOSFETs is given. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (0001) and (1120) faces. In the fabricated MOSFETs, SCEs such as punchthrough behavior, decrease of threshold voltage, deterioration of subthreshold characteristics, and saturation of transconductance occur by reducing channel length. The critical channel lengths below which SCEs occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths obtained from the device simulation is in good agreement with the empirical relationship for Si MOSFETs. The critical channel lengths in the fabricated SiC MOSFETs are slightly longer than simulation results. The dependence of crystal face orientations on SCEs is hardly observed. Impacts of interface charge on the appearance of SCEs are discussed.