Increase of gate capacitance in DMOST

The gate capacitance of an n-channel DMOST at nonzero drain current biasing exceeds that of a similar conventional MOST and may even exceed the gate oxide capacitance. This effect is due to the behavior of mobile electrons in the device. The fundamental operation of the DMOST is understood through the use of a two-dimensional computer analysis. Based on this insight, the increase of the gate capacitance is clarified in terms of the electron velocity between the source and the drain. Gate capacitance measurements are carried out on experimental DMOST's, which are made on a p^-background as well as on an n^-epitaxial layer. The measuredC-Vcurves qualitatively confirm the theory on the increase of the gate capacitance in its dependence on the background of the DMOST and the applied dc voltages.     

Model for DMOST threshold voltage

An analytical model for the channel region in MOS-gated power transistors has been developed. The model takes into account the effect of substrate doping gradient on the threshold voltage of the transistor and it can be applied to lateral and vertical DMOS and IGBT transistor structures. The model has been tested by comparing the calculated I-V characteristics for an MOS structure having various doping gradients to the results from a 2-D device simulator.<>     

A novel GaAs power MESFET with low distortion characteristicsemploying semi-insulating setback layer under the gate

A low distortion GaAs power MESFET has been developed by employing a semi-insulating setback layer under the gate. The setback region was obtained by diffusing chromium from the Cr/Pt/Au gate metal in self-aligned manner. The novel power FET with the setback layer was found to be insensitive to surface trapping effects. They showed only 5-6 percent frequency dispersion of drain current at 1 MHz compared to DC condition. Because of this small frequency dispersion, the typical measurement FET, which has a surface setback layer, with a gate width of 36 mm exhibited 1.5 dB larger output power at 1 dB gain compression point than that of the FET without the setback layer. Moreover, in the π/4 shift-QPSK modulation that has been most popular in digital mobile communication system, the FET exhibited 11 dB smaller adjacent channel leakage power than the conventional one at the output power of 31.5 dBm     

Resistive parametric mixing in GaAs oscillators at microwave frequencies

Resistive mixing in GaAs between a suitably biased microwave pump signal and a small signal at the first subharmonic of the pump is shown to result in an effective negative mobility at the signal frequency. The implications are discussed.     

Fast current control for low harmonic distortion at low switchingfrequency

The structure of the current control loop of an induction machine drive determines decisively the dynamic performance of the overall system. Fast current control is a prerequisite for dynamic decoupling between the torque and the flux commands. Standard solutions are well established for drives in the low- and medium-power ranges. The low switching frequency of high-power pulsewidth modulation inverters calls for a tradeoff in controller design between the low harmonic losses and torque ripple in the steady state on one hand, and fast dynamic response during the transients on the other. The problem is developed in detail. A variable-structure approach is proposed as the solution     

Nonlinear distortion and mixing processes in field-effect transistors

From the transfer characteristic of the junction-type field effect transistor, nonlinear distortion effects can be evaluated without difficulty. It is shown how the conversion transconductance can be calculated as a function of the operating point, the local oscillator voltage and the oscillator output resistance. A new method has been derived which permits a very precise evaluation of the conversion transconductance even if the operating point is chosen in the cutoff region. The investigations deal with the influence of the signal amplitude upon nonlinear distortion in mixer stages and also treat the generation of whistles. The conversion transconductance exhibits a flat maximum as a function of the gate bias voltage. Thus, an optimum operating range can be indicated where the ratio between mixing current and distortion product currents is most favorable. Finally, it is shown how the operating point can be preserved in stabilized mixer stages and some reference details for the behavior of FET stages at very high frequencies are given.     

Transistor design for low distortion at high frequencies

The design of high-frequency bipolar transistors with very low distortion is described. Simple expressions for distortion are used to select device parameters for the optimization of distortion performance. The effect of epitaxial-layer characteristics on device performance is considered in detail, and the importance of collector depletion in achieving low distortion is shown. The influence of device geometry on distortion is considered, and the degradation caused by MOS capacitance is illustrated.     

利用四波混频消除图像畸变的局限性

一、引言 在大多数理论研究中,人们仅在平面泵浦和探测波的条件下研究四波混频产生位相共扼波的机理、手段。然而在实际应用简并四波混频共轭波补偿大气干扰时,入射到位相共轭镜上的探测波不可能是理想平面波。但是在大多用相位共轭消畸变的方案中都忽略了畸变探测波在简并四波混频中产生什么样的“共轭波”这个问题。本文将讨论利用简并四波混频消除通过湍流大气传输图像的畸变问题。     

Millimeter-resolution optical time-domain reflectometry using afour-wave mixing sampling gate

We report an optical time-domain reflectometer that employs an ultrafast optical switch based on nondegenerate four-wave mixing in a semiconductor laser amplifier. Two-point spatial resolution on the order of 1 mm over 2 m is demonstrated; Fresnel reflections with optical return losses greater than 53 dB are detected. Submillimeter-resolution optical time-domain reflectometry over a 100-m range should be possible with modifications to the pulse sources     

A low distortion bipolar mixer for low voltage direct up-conversionand high IF systems

This paper describes the implementation of a low distortion mixer for direct up-conversion and high IF systems. A Gilbert cell with a low distortion transconductance constitutes the mixer core. A current feedback loop is used to linearize the transconductance stage, achieving an alternate channel leakage of -71 dBc with a power penalty of 15%. The mixer operates from 2.7 to 7.5 V of supply voltage and over a temperature range of -40 to 85°C. It provides -3 dBm output power while drawing 7.5 mW from a 3-V supply. The mixer is implemented in 1-μm BiCMOS for a global system for mobile communications (GSM) chip set     

Frequency division with low FM distortion

The FM distortion properties of a fast frequency dividing flip-flop are measured and are found to be very low and suitable for use in a new type of solid-state microwave radio repeater.     

Copper gate AlGaN/GaN HEMT with low gate leakage current

Copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current were demonstrated. For comparison, nickel/gold (Ni/Au) gate devices were also fabricated with the same process conditions except the gate metals. Comparable extrinsic transconductance was obtained for the two kinds of devices. At gate voltage of -15 V, typical gate leakage currents are found to be as low as 3.5/spl times/10/sup -8/ A for a Cu-gate device with gate length of 2 /spl mu/m and width of 50 /spl mu/m, which is much lower than that of Ni/Au-gate device. No adhesion problem occurred during these experiments. Gate resistance of Cu-gate is found to be about 60% as that of NiAu. The Schottky barrier height of Cu on n-GaN is 0.18 eV higher than that of Ni/Au obtained from Schottky diode experiments. No Cu diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. These results indicate that copper is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMT.     

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level.     

An adaptive noise canceller with low signal distortion for speechcodecs

This paper proposes an adaptive noise canceller (ANC) with low signal distortion for speech codecs. The proposed ANC has two adaptive filters: a main filter (MF) and a subfilter (SF). The signal-to-noise ratio (SNR) of input signals is estimated using the SF. To reduce signal distortion in the output signal of the ANC, a step size for coefficient update in the MF is controlled according to the estimated SNR. Computer simulation results using speech and diesel engine noise recorded in a special-purpose vehicle show that the proposed ANC reduces signal distortion in the output signal by up to 15 dB compared with a conventional ANC. Results of subjective listening tests show that the mean opinion scores (MOSs) for the proposed ANC with and without a speech codec are one point higher than the scores for the conventional ANC     

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF₂-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (V_th) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μ_eff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (J_g) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μ_eff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the J_g and robustness against reverse-bias stressing.     

A bulk-driven quasi-floating gate FVF current mirror for low voltage,low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.     

Motion estimation with low resolution distortion metric

Considering all possible candidate motion vectors in a given search area and calculating a distortion measure at every search position, as with the full-search block-matching motion estimation algorithm (FSBME), places a prohibitively high computational burden on the video encoder, making it unsuitable for real-time/portable video applications. To reduce computational complexity while maintaining accuracy, a new version of the reduced-bit, sum of absolute difference (RBSAD) algorithm is presented, which allows for optional correction to full resolution (FSBME) when appropriate. Analysis of a number of video sequence shows that this correction is required for blocks for which there is little motion between frames.     

Analysis of band-to-band mixing distortion contributions in some usual circuit topologies

This paper uses hand analysis and a new fully numerical distortion contribution analysis technique to explain and optimize the nonlinear performance of analog circuits. Several example circuits are studied, where mixing of nonlinear distortion from one harmonic band to another is important. In some circuits the band-to-band mixing can be employed to reduce the overall distortion.     

High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm². Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique