Resistive element using depletion mode MOSFETs

A two-terminal resistive element consisting of depletion-mode MOSFETs is described. This circuit can provide a combination of large resistance and extended range of linearity when compared with individual depletion-mode loads. A small-signal AC analysis has been performed to relate the frequency response of the element to the electrical parameters of the transistors and to the operating point. The circuit has been fabricated in thin-film silicon-on-sapphire and its operation demonstrated.<>     

Simulation of the accumulation-punchthrough mode in depletion MOSFETs

An analytical model is developed for a depletion MOSFET with a built-in channel operating in the accumulation-punchthrough mode. The model equations take into account several important effects associated with this mode of operation, including charge sharing between the channel and the source and drain regions. Closed-form expressions are derived for the output I–V characteristics, drain conductance in the linear region, and gate and substrate transconductances in the saturation region. Useful equations for the threshold and saturation voltages are also provided. High accuracy of the model is confirmed by the experimental results.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

Behavior of electrically small depletion mode MOSFETs at low temperature

Impurity freezeout has a substantial effect on the threshold and subthreshold characteristics of large depletion mode devices. Recent experiments on short and narrow channel depletion mode devices demonstrate that geometry effects are independent of temperature and comparable to those of enhancement mode devices. Reduction of the electrical device size does not alter the degree of impurity freezeout. To predict the behavior of small channel enhancement and depletion mode devices, freezeout effects and geometry effects can be directly superimposed. A simple qualitative model is used to describe the conditions under which the superposition is valid.     

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs

Ion implantation, followed by annealing process, often leads to nonuniform doping and considerable depletion effect in the polysilicon gate of submicron MOS devices. Such an effect can alter notably the subthreshold characteristics and invalidate the conventional subthreshold current model. This paper studies the polysilicon-gate depletion effects on the subthreshold behavior based on results obtained from two-dimensional device simulation. An empirical expression is also suggested to describe the subthreshold current including the depletion effect.     

Relationship between short channel behavior and long term stability of n-channel enhancement and depletion MOSFETs

Enhancement and depletion mode n-channel MOSFETs are investigated with respect to short channel effects and hot carrier related instabilities. It is found that subthreshold characteristics of normally off type devices are improved by additional deep channel implants. However, long term stability of enhancement mode devices decreases with the deep channel implant dose. A similar behavior is observed for depletion mode devices. Significant improvement in device stability can be realized using buried channel conduction. However, short channel effects attain untolerable magnitudes in devices with deep buried channels. It is concluded in this paper, that the conventional approaches used for optimization of long term stability and d.c. characteristics of small size MOSFETs are technologically incompatible. In the outlook, device design requirements are discussed to circumvent these problems.     

CAD model for threshold and subthreshold conduction in MOSFETs

The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion. The proposed model shows better agreement to experimental results than previous models in the subthreshold and threshold regions, and is well suited for use in circuit simulation programs; the authors have implemented it in MSINC and SPICE programs, and simulation results are compared to experimental data for a micropower amplifier.     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

Understanding threshold voltage in undoped-body MOSFETs: An appraisal of various criteria

Undoped-body MOSFETs are currently becoming increasingly important and the value of threshold voltage is often used to assess the reliability of fabricated devices. However there exists a disparity of threshold voltage criteria proposed for these novel devices. The concept of threshold voltage in undoped-body MOSFETs is examined and various existing criteria are analyzed and compared in an effort to clarify the ambiguity of the meaning of threshold and understand its dependence on technological parameters in these devices. Phenomenological considerations are also presented to shed light on the behavior of the sub-threshold slope with changing semiconductor body thickness.     

Two-dimensional threshold voltage analytical modes of DMG strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further,the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.     

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain ...     

异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*

本文首次并建立了异质栅全耗尽型应变Si SOI (DMG SSOI) MOSFET的二维表面势沿沟道变化的模型．并对该结构的MOSFET的短沟道效应SCE (short channel effect),热载流子效应HCE(hot carrier effect),漏致势垒降低DIBL (drain induced barrier lowering)和载流子传输效率进行了研究．该模型中考虑以下参数：金属栅长,金属栅的功函数,漏电压和Ge在驰豫SiGe中的摩尔组分．结果表明沟道区的表面势引进了阶梯分布,正是这个阶梯分布的表面势抑制了SCE,HCE和DIBL．同时,应变硅和SOI(silicon-on-insulator)结构都能提高载流子的传输效率,特别是应变硅能提高载流子的传输效率．此外阈值电压模型能者正确表明阈值电压随栅长比率L2/L1减小或应变Si膜中Ge摩尔组分的降低而升高．数值模拟器ISE验证了该模型的正确性．     

Avalanche behavior of low-voltage power MOSFETs

This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance (R/sub DSon/). A novel test setup is proposed to measure "avalanche" resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs.Different short channel field effects,such as fringing fields,junction-induced lateral fields and substrate fields,are carefully investigated,and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model.Through analytical model-based simulation,the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations.Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model.The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET.The short channel effects are found to be reduced in an SON,thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope.This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs

A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs. Different short channel field effects, such as fringing fields, junction-induced lateral fields and substrate fields, are carefully investigated, and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model. Through analytical model-based simulation, the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations. Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model. The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET. The short channel effects are found to be reduced in an SON, thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope. This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.     

Device and process simulation of SOS and SOI MOSFETs

The 3D modeling of thin-film structures used in SOS and SOI MOSFETs with different geometries is discussed. For such devices a computer simulation of electrical performance is run with the ISE TCAD simulator. A comparison with experimental results is made. Ways to increase the accuracy of the underlying model are considered.     

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements