Resistive element using depletion mode MOSFETs

A two-terminal resistive element consisting of depletion-mode MOSFETs is described. This circuit can provide a combination of large resistance and extended range of linearity when compared with individual depletion-mode loads. A small-signal AC analysis has been performed to relate the frequency response of the element to the electrical parameters of the transistors and to the operating point. The circuit has been fabricated in thin-film silicon-on-sapphire and its operation demonstrated.<>     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

Behavior of electrically small depletion mode MOSFETs at low temperature

Impurity freezeout has a substantial effect on the threshold and subthreshold characteristics of large depletion mode devices. Recent experiments on short and narrow channel depletion mode devices demonstrate that geometry effects are independent of temperature and comparable to those of enhancement mode devices. Reduction of the electrical device size does not alter the degree of impurity freezeout. To predict the behavior of small channel enhancement and depletion mode devices, freezeout effects and geometry effects can be directly superimposed. A simple qualitative model is used to describe the conditions under which the superposition is valid.     

Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs

Ion implantation, followed by annealing process, often leads to nonuniform doping and considerable depletion effect in the polysilicon gate of submicron MOS devices. Such an effect can alter notably the subthreshold characteristics and invalidate the conventional subthreshold current model. This paper studies the polysilicon-gate depletion effects on the subthreshold behavior based on results obtained from two-dimensional device simulation. An empirical expression is also suggested to describe the subthreshold current including the depletion effect.     

Relationship between short channel behavior and long term stability of n-channel enhancement and depletion MOSFETs

Enhancement and depletion mode n-channel MOSFETs are investigated with respect to short channel effects and hot carrier related instabilities. It is found that subthreshold characteristics of normally off type devices are improved by additional deep channel implants. However, long term stability of enhancement mode devices decreases with the deep channel implant dose. A similar behavior is observed for depletion mode devices. Significant improvement in device stability can be realized using buried channel conduction. However, short channel effects attain untolerable magnitudes in devices with deep buried channels. It is concluded in this paper, that the conventional approaches used for optimization of long term stability and d.c. characteristics of small size MOSFETs are technologically incompatible. In the outlook, device design requirements are discussed to circumvent these problems.     

CAD model for threshold and subthreshold conduction in MOSFETs

The authors propose a simple model for the operation of MOSFETs in both weak and strong inversion. The proposed model shows better agreement to experimental results than previous models in the subthreshold and threshold regions, and is well suited for use in circuit simulation programs; the authors have implemented it in MSINC and SPICE programs, and simulation results are compared to experimental data for a micropower amplifier.     

Modelling the threshold voltage of short-channel silicon-on-insulator MOSFETs

A simple analytical model for the threshold voltage of short-channel, thin-film, fully-depleted silicon-on-insulator MOSFETs is presented. The model is based on the analytical solution for the two-dimensional potential distribution in the silicon film, which is taken as the sum of the long-channel solution to the Poisson equation and the short-channel solution to the Laplace equation. The model shows close agreement with numerical PISCES simulation results. The equivalence between the proposed model and the parabolic model of Young (1989) is also proven.<>     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

Avalanche behavior of low-voltage power MOSFETs

This letter addresses the behavior of low voltage power MOSFETs under avalanche, with a paralleling point of view. It is shown that during avalanche, up-to-date technology MOSFET transistors exhibit a resistance far in excess of their on-state resistance (R/sub DSon/). A novel test setup is proposed to measure "avalanche" resistance. A simple model of breakdown voltage is then proposed. It becomes possible to perform fast simulations using this model to study current balance between paralleled transistors under avalanche operation. It is shown that considering avalanche resistance reduces the influence of breakdown voltage mismatches and allows for better current sharing.     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

Device and process simulation of SOS and SOI MOSFETs

The 3D modeling of thin-film structures used in SOS and SOI MOSFETs with different geometries is discussed. For such devices a computer simulation of electrical performance is run with the ISE TCAD simulator. A comparison with experimental results is made. Ways to increase the accuracy of the underlying model are considered.     

Temperature and annealing effects on InAs nanowire MOSFETs

We report on temperature dependence on the drive current as well as long-term effects of annealing in vertical InAs nanowire Field-Effect Transistors. Negatively charged traps in the HfO₂ gate dielectric are suggested as one major factor in explaining the effects observed in the transistor characteristics. An energy barrier may be correlated with an un-gated InAs nanowire region covered with HfO₂ and the effects of annealing may be explained by changed charging on defects in the oxide. Initial simulations confirm the general effects on the I-V characteristics by including fixed charge.     

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/相似文献   

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements     

Temperature dependence of turn-on voltage of gold-doped MOSFETs

The temperature dependence of the turn-on voltage of gold-doped and control n- and p-channel MOSFETs has been measured. To account for the large positive shift of turn-on voltage, VT Au, of gold treated n- and p-channel devices, it has been proposed that the gold eliminates the fast interface traps of continuous energy distribution, and that additional acceptor states very close to the valence band can cause additional charge QA Au, which can dominate the effect of acceptor and donor levels of gold ions in the silicon surface space charge region, and can also over-compensate the surface state charge, Qss. To fit the theoretical VT Auversus T curve to experimental curves, an accumulation of electrically active gold within the surface space charge region has been considered in n-channel devices and depletion in p-channel devices.     

Analytical models of subthreshold swing and threshold voltage forthin- and ultra-thin-film SOI MOSFETs

Analytical models are proposed for thin- and ultra-thin film silicon-on-insulator (SOI) MOSFETs operating in weak or strong inversion. The models take into account all the device parameters. The cases of two and three interfaces with a silicon substrate are considered in the modeling and compared with one another. These models give the main electrical MOSFET parameters in ohmic operation (subthreshold swing and threshold voltage) for these structures. The basic approximation is the consideration of a linearly varying potential in the Si film, which has been inferred on the basis of numerical simulations. Various behaviors depending on the Si film and the buried insulator thickness as well as the interface charges, Si film doping, or substrate regime are simulated to assess the properties and the performances of SOI MOS transistors and to validate the analytical models     

A process-parameter-based circuit simulation model forion-implanted MOSFETs and MESFETs

It is shown that the correct-equivalent-box representation of implanted doping profiles, derived in terms of the process parameters by matching the charge-voltage relationships of the actual profile and the box profile, can be used for accurately simulating the electric characteristics of surface-channel MOSFETs and MESFETs having implanted channels. Because the correct box representation is known directly in terms of the doping profile parameters, which can be obtained from process simulation, the need for experimental determination of the box is obviated. The application of the model can substantially reduce the number of experimental trial-and-error iterations involved in the development of devices and circuits. The correct box is also applicable to the CCDs whose physics of operation is similar to that of MOSFETs     

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.     

Comparison of threshold modulation in narrow MOSFETs with different isolation structures

The threshold shifts of narrow MOSFETs with different oxide structures are calculated explicitly using numerical means. It is found that the semirecessed device with vertical-field oxide step and vertical side wall appears to be a more suitable candidate for very-large-scale integration (VLSI) if the characteristic of threshold change vs gate width is taken into consideration.