Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.     

Novel Viterbi decoder VLSI implementation and its performance

An advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation is presented. Two novel circuit design schemes have been proposed: scarce state transition (SST) decoding and direct high-coding-rate convolutional code generation and variable-rate decoding. SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading error probability performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS device. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSIs in the rate one-half mode imposed by the thermal limitation. The other Viterbi decoding scheme makes it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25-Mb/s) and universal-coding-rate Viterbi decoder VLSIs have been developed     

A 2-kbit superconducting memory chip

A 2-kb nondestructive readout memory chip has been built using an Nb/AlO_x/Nb Josephson-junction process with a 2.5-μm design rule. A bitmap of 56% functional cells among 1.5 K tested cells, a read access time of 200 ps, an average cycle time of 500 ps without the decoder, and a power dissipation of 1.6 mW including peripheral circuits have been obtained. The decoding time is estimated to be 540 ps. The circuits in this 5-mm by 5-mm, 24-pin chip includes 2 K memory cells, 6-b decoder and drivers, serial-to-parallel and parallel-to-serial converters, and circuits for design of testability or timing measurements. More than 14000 junctions are used on the chip     

An Area-Effective Cell-Based Channel Decoder LSI For a Digital Satellite TV Broadcasting

A new channel decoder LSI, which will be used in digital satellite TV broadcasting Set-Top Boxes, has been designed. This LSI's functions include AD/DA conversion, QPSK demodulating, Viterbi decoding, frame synchronization, convolutional deinterleaving, Reed-Solomon (RS) decoding, and descrambling. We use a new method for Viterbi Decoding called the Tracking Survivor State Information (TSSI) method, which not only reduces power consumption, but also solves the problem of increasing memory size. To reduce the size of RS decoder circuit, we used a three-stage-pipeline structure as well as designed a new architecture to realize Euclid's algorithm. This device has been fabricated in a 0.35 µm 3-metal CMOS standard cell-based process and is composed of 670 K transistors. In this paper, we describe the TSSI method of the Viterbi Decoder and the Reed-Solomon Decoder's new 3-stage pipeline architecture.     

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes

In this paper, we propose a low complexity decoder architecture for low-density parity-check (LDPC) codes using a variable quantization scheme as well as an efficient highly-parallel decoding scheme. In the sum-product algorithm for decoding LDPC codes, the finite precision implementations have an important tradeoff between decoding performance and hardware complexity caused by two dominant area-consuming factors: one is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of the nonlinear function Ψ(x). The proposed variable quantization schemes offer a large reduction in the hardware complexities for LUT and memory. Also, an efficient highly-parallel decoder architecture for quasi-cyclic (QC) LDPC codes can be implemented with the reduced hardware complexity by using the partially block overlapped decoding scheme and the minimized power consumption by reducing the total number of memory accesses for updated messages. For (3, 6) QC LDPC codes, our proposed schemes in implementing the highly-parallel decoder architecture offer a great reduction of implementation area by 33% for memory area and approximately by 28% for the check node unit and variable node unit computation units without significant performance degradation. Also, the memory accesses are reduced by 20%.     

AC-and DC-powered subnanosecond 1-kbit Josephson cache memorydesign

The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators     

A memory efficient parallel layered QC-LDPC decoder for CMMB systems

This paper presents a memory efficient architecture of layered decoder for the dual-rate LDPC codes in the China Multimedia Mobile Broadcasting (CMMB) system. An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced. At the same time, the memory structure keeps the “one cycle one layer access” timing schedule to achieve high decoding throughput. Furthermore, the early termination strategy is employed to further increase the throughput; a non-uniform quantization scheme and an area efficient calculation module are developed to further improve the memory efficiency and hardware resource efficiency, respectively. By using SMIC 130 nm 1P7M CMOS process, the decoder is implemented and the core area is 5.29 mm². The total memory bits consumption is only 130.5 K which consumes 2.53 mm² memory area.     

A Real-Time Video Decoder for Digital HDTV

In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

Low-power data transfer and storage exploration for H.263 videodecoder system

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data-transfer scheme in the specification, and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst case mode using predicted (P) frames, memory power consumption is reduced by a factor of 7 when compared to the reference design. For the worst case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment     

Circuit techniques for large CSEA SRAMs

The CMOS-storage emitter-access (CSEA) memory cell offers faster access than the MOS cells used in conventional BiCMOS SRAMs but using it in large memory arrays poses several problems. Novel BiCMOS circuit approaches to address the problems of decoding power, electronic noise, level translation, and write disturbance are described. Results on a 64-kb CSEA SRAM using these techniques are reported. The device, fabricated in an 0.8-μm BiCMOS technology, achieves read access and write pulse time of less than 4 ns while dissipating 1.7 W at a case temperature of 70°C     

Low-power log-MAP decoding based on reduced metric memory access

Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards such as W-CDMA and CDMA2000. Although several low-power techniques have been proposed, power consumption is still a major issue to be solved in practical implementations. Since turbo decoding is classified as a memory-intensive algorithm, reducing memory accesses is crucial to achieve a low power design. To reduce the number of memory accesses for maximum a posteriori (MAP) decoding, this paper proposes an approximate reverse calculation method that can be implemented with simple arithmetic operations such as addition and comparison. Simulation results show that the proposed method applied to the W-CDMA standard reduces the access rate of the backward metric memory by 87% without degrading error-correcting performance. A prototype log-MAP decoder based on the proposed reverse calculation achieves 29% power reduction compared to a conventional decoder that does not use the reverse calculation.     

A fast multispeed comma-free Reed-Solomon decoder for W-CDMA applications using foldable systolic array architecture

This brief proposes a fast multispeed comma-free Reed-Solomon (CFRS) decoder for the frame synchronization and code-group identification in the cell search of the Third Generation Partnership Project wide-band code-division multiple access/frequency division duplexing (W-CDMA/FDD) system. A foldable systolic array is proposed to achieve fast decoding and provide flexible tradeoffs between power consumption, chip size, and decoding latency. Multispeed decoding, an idea that is useful for cell search in different application scenarios, can also be achieved with the same array architecture. The proposed CFRS decoder is implemented in a 3.3-V 0.35-/spl mu/m CMOS technology with 2.2 /spl times/ 2.2 mm/sup 2/ core area and power dissipation of 13.3 and 1.23 mW in high- and low-speed decoding modes, respectively.     

High-performance Viterbi decoder with circularly connected 2-D CNN unilateral cell array

A very-high-performance Viterbi decoder with a circularly connected two-dimensional analog cellular neural network (CNN) cell array is disclosed. In the proposed Viterbi decoder, the CNN cells with nonlinear unilateral connections are implemented with electronic circuits at nodes on a trellis diagram. The circuits are circularly connected, forming a cylindrical shape so that the cells of the last stage are connected to those of the first stage. Unilateral connections guide the information to flow circularly around the cylindrical surface. Such configuration enables the conceptually infinite length of the trellis diagram to be reduced to a circuit of limited size. The analog circuits does not require any analog-digital converters, which is the major cause of high power consumption and the quantization error. With the parallel analog processing structure, its decoding speed becomes very high. Also, the decoding mechanism using triggering wave of the CNN circuit does not require the path memory. Circuits for the proposed structure have been designed with HSPICE. Features of the proposed Viterbi decoder are compared with those of the conventional digital Viterbi decoder.     

Energy Efficient VLSI Architecture for Linear Turbo Equalizer

In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30–60% and 10–60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.     

An asynchronous GaAs MESFET static RAM using a new current mirrormemory cell

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm² and cell current of 60 μA were achieved using a conventional E/D process     

A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme