Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

High-frequency on-chip inductance model

The effect of random signal lines on the on-chip inductance is quantitatively investigated, using an S-parameter-based methodology and a full wave solver, leading to an empirical model for high-frequency inductance. The results clearly indicate that the random signal lines as well as designated ground lines provide return paths for gigahertz-frequency signals. In particular, quasi TEM-wave-like propagation mode is observed above 10 GHz, revealing a unique relationship between capacitance and inductance of the signal line. Incorporating the random capacitive coupling effect, our frequency-dependent RLC model is confirmed to be valid up to 100 GHz.     

Surface Current Modelling of the Skin Effect for On-Chip Interconnections

In this paper, the skin effect for 2-D on-chip interconnections is predicted using a recently developed differential surface admittance concept. First, the features of the new approach are briefly recapitulated and details are given for a conductor with rectangular cross-section. Next, the 1-D situation is studied as a limiting case of the 2-D situation. The relationship with a local impedance formulation is investigated and illustrated with a numerical example. Finally, the new method is used to determine inductance and resistance matrices of 2-D on-chip interconnect examples with specifications taken from the international technology roadmap for semiconductors. Extra capacitance data are also provided.     

An empirical three-dimensional crossover capacitance model formultilevel interconnect VLSI circuits

We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 μm and wire thickness down to 0.15 μm. The model is useful for VLSI design and process optimization     

Inductance calculation of 3D superconducting structures

We propose a method for inductance calculation of three-dimensional superconducting structures by using software designed for high-frequency normal metal cases. By examining the analytical expressions for the current density distributions of the same ideal parallel plane structure in both the high-frequency normal metal case and the superconductor case, we obtain a correction factor for the kinetic inductance calculation in the latter. It is then assumed that this correction factor can be applied to real superconducting layers with finite widths. The total inductance of any superconducting structure can be obtained by finding the magnetic field energy in the high-frequency normal metal case with the same configuration, and adding the kinetic energy with the correction factor applied. Normal metal field simulators, such as MAXWELL, can readily be used. A SQUID loop inductance is simulated as a test case on MAXWELL, and 3% agreement is achieved with the experimental result.     

Inductance-controlled electroabsorption Modulator modules using the flip-chip bonding technique

The wire-bonding technique is widely used for the connections between the electroabsorption (EA) modulator chips and the electrical signal transmission lines. However, the parasitic inductance of the bonding wire degrades the electrical characteristics of the EA modulator modules in a high-frequency region. In this paper, we theoretically analyze the influence of parasitic inductance on the base-band digital transmission and obtain the relationship between the EA modulator capacitance and the optimum lead inductance. For precise inductance control, we introduced the flip-chip bonding (FCB) technique and fabricated 40-Gb/s EA modulator modules.     

A Wideband Scalable and SPICE-Compatible Model for On-Chip Interconnects Up to 110 GHz

A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to 110 GHz is presented in this paper. The series branches of the proposed multisegment model consist of an RL ladder network to capture the skin and proximity effects, as well as the substrate skin effect. Their values are obtained from a technique based on a modified effective loop inductance approach and complex image method. A CG network is used in the shunt branches of the model, which accounts for capacitive coupling through the oxide and substrate loss due to the electrical field, as well as the impact of dummy metal fills. The values of these elements are determined by analytical and semiempirical formulas. The model is validated by a full-wave electromagnetic field solver, as well as measurements. The simulated S-parameters of the model agree well with the measured S-parameters of on-chip interconnects with different widths and lengths over a wide frequency range from dc up to 110 GHz.     

SiGe HBT Microprocessor Core Test Vehicle

A major impediment to the continuation of Moore's Law in the years to come is the performance of interconnections in ICs at high frequencies. Microprocessors are using a greater portion of their clock cycle charging and discharging interconnections. Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) provide a fast track technology for the exploration of the effect of interconnections on high-speed computer design. Industry has pursued low-k dielectrics to decrease wire capacitance. Cu metallization has been used to reduce wire resistance which becomes important as the wire dimensions are scaled down. These are not the only issues for high-frequency interconnections. Some other high-frequency issues include coupling, transmission line propagation, skin effects, and dielectric and substrate loss. These phenomena cause signal attenuation, noise, and dispersion in addition to delay. In the limit of zero device delay, interconnection delay will remain in addition to these problems. Wire shortening has been possible using more layers of interconnections, but this approach may be reaching its limit. An unconventional approach, three-dimensional (3-D) integration, attempts to shorten wiring through increased circuit component placement flexibility. The approach considered here for 3-D integration uses wafer-to-wafer aligning and bonding, wafer thinning and deep, high-aspect-ratio Cu via formation. This provides an intimate interconnection between CPU components and an extremely wide path to memory that would be infeasible in conventional or multichip module packaging. This combination of SiGe HBT BiCMOS and 3-D chip stack technologies enables small computing engines in the 16-32-GHz range.     

Use of test structures for characterization and modeling of inter and intra-layer capacitances in a CMOS process

In this paper, we present a global approach for inter- and intralayer capacitance characterization and modeling. Using an accurate on-chip measurement method, we have characterized realistic test patterns, i.e., test patterns consistent with capacitive couplings encountered in a layout. These reference values have allowed us to point out some limitations of current models and to propose new simple analytical models suitable for small dimension capacitive patterns. This paper emphasizes inter- and intralayer modeling     

Microwave frequency interconnection line model of a wafer level package

In this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the /spl mu/BGA package, but longer propagation delay, because of the relatively high package capacitance.     

Inductance effect in crosstalk prediction

Rapid progress in integrated circuit technology has led to an increase in switching speeds of digital circuits. This increase is the primary reason why inductance noise causes chips to fail. As a result, there is a growing interest in the inductance associated with on-chip signal lines. In this paper, we present the electromagnetic analysis we have followed in order to determine the accurate values of the R,L,C,G equivalent parameters from which a set of multiple coupled transmission lines could be modeled. We then determine the most critical parameters which make the inductance effect important and we propose a new analytical expression to accurately evaluate the crosstalk voltage.     

Statistical extraction and modeling of inductance considering spatial correlation

In this paper, we present a novel method for statistical inductance extraction and modeling for interconnects considering process variations. The new method, called statHenry, is based on the collocation-based spectral stochastic method where orthogonal polynomials are used to represent the statistical processes. The coefficients of the partial inductance orthogonal polynomial are computed via the collocation method where a fast multi-dimensional Gaussian quadrature method is applied with sparse grids. To further improve the efficiency of the proposed method, a random variable reduction scheme is used. Given the interconnect wire variation parameters, the resulting method can derive the parameterized closed form of the inductance value. We show that both partial and loop inductance variations can be significant given the width and height variations. This new approach can work with any existing inductance extraction tool to extract the variational partial and loop inductance or impedance. Experimental results show that our method is orders of magnitude faster than the Monte Carlo method for several practical interconnect structures.     

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.      

Return Path Assumption Validation for Inductance Modeling in Digital Design

Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing prelayout effective inductance estimations are suggested.     

Substrate Effects on Resonant Frequency of Silicon-Based RF On-Chip MIM Capacitor

This brief presents an analytical model that describes a silicon-based RF on-chip metal-insulator-metal (MIM) capacitor including the parasitics originating from its coupling with backend intermetal dielectric (IMD) scheme and the substrate. Results show that the resonant frequency f_re depends on the intrinsic capacitance, inductance, and substrate effects of the MIM. The model and f_re formula are verified experimentally for several types of MIM capacitors (i.e., high kappa and Si₃N₄ based) integrated on different IMDs (e.g., undoped glass and low kappa). The results also show that for a given C_MIM, if the capacitance density is increased further so that the area is shrunk, and the inductances are reduced to a level that is comparable to the substrate effects from item epsiv₀epsiv_rrho_Si h_eff|SiR₂/h_eff|IMD, then further f_re improvement could be limited     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.     

Synthesis of three-dimensional light fields and applications

The possibility of synthesizing light fields satisfying given requirements within a three-dimensional (3-D) space domain was proposed and demonstrated during recent years. In this paper we present fundamental physical properties characterizing 3-D fields and propose analytical and numerical procedures to synthesize them. These methods solve the proper wave equation under 3-D constraints. Since the manipulation of light is a basic task, this is an effective approach to deal with classical as well as novel problems in optics and photonics technologies. We discuss exciting new potential areas of application and extensions of this concept     

Finite-Difference Analysis of EMP Coupling to Thin Struts and Wires

This paper describes the implementation of the thin-strut formalism in the 3-D EMP time-domain finite-difference code THREDE. The thin-strut formalism permits inclusion of arbitrary fine wires in THREDE without imposing any corresponding demand to reduce the cell size to the wire size. The keystone of this technique is the so-called in-cell inductance-the inductance per unit length a thin wire would have with respect to an enclosing conductor half a cell removed. THREDE results using this formalism are compared with analytic EMP solutions for a linear dipole antenna and a loop antenna. Errors are around 10 percent for the loop and 7 percent for the dipole. The 10-percent loop error could probably be improved; the 7-percent dipole error seems to be fundamental to the basic THREDE approximations.