Unique ESD failure mechanisms during negative to Vcc HBM tests

HBM ESD tests on two types of 0.6 μm DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground. These failures occurred at lower than expected ESD stress voltages due to power-up circuit interactions that either turned-on unique internal parasitic ESD current paths or disrupted the normal operation of the output pin’s ESD protection circuit. ESD analysis found there exists a set of power-up sensitive circuits and if placed near a Vcc bond pad can result in low voltage ESD failures.     

The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's

The objective of this paper is to discuss the characteristics of SOI nMOSFET's that can be exploited to clamp HBM ESD stresses and to explain the related failure modes and mechanism observed in these devices. The influence on the HBM ESD protection capability of the first order main parameter: the nMOSFET gate length is investigated. The ESD protection capability for both positive and negative polarity HBM stresses is elaborated and compared. The ESD clamping and device failure mechanisms limiting the ESD protection performance are identified.     

Analysis of lateral DMOS power devices under ESD stress conditions

The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogeneous current flow due to the unusual electrical behavior are accurately analyzed in single- and multi-finger devices     

Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions

Time-dependent dielectric breakdown of 2.2–4.7 nm gate oxides is investigated down to the nanosecond time regime. The so-called 1/E model best fits the time-to-breakdown data. Latent damage is also examined and it is seen that the trap generation rate, i.e., the damage rate, is pulse-width dependent, and, thus, d.c. data should not be used to predict the degradation rate under ESD-type stress conditions. Voltage overshoots and a slow turn-on time make low voltage triggered silicon controlled rectifiers bad candidates for protecting the ultra-thin gate oxide against CDM stress.     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

High reliability electronic devices need to sustain thousands of electrostatic discharge (ESD) stresses during their lifetime. In this paper, it is demonstrated that repetitive ESD stresses on a protection device such as a bidirectional diode induce progressive defects into the silicon bulk. With “Sirtl etch” failure analysis technique, the defects could be localized quite precisely at the peripheral in/out junctions. The degradation mechanisms during repetitive IEC 61000-4-2 pulses have been investigated on a protection diode with the objective of improving the design for sustaining 1000 pulses at 10 kV level.     

电声器件测试仪类仪器的校准方法研究

在电子科技和通信技术的发展与推动下,电声器件的种类和技术得到了发展与创新,并且逐渐应用到更加广泛的领域当中。通过测试仪器对电声器件的性能进行测试,是保证和发挥电声器件性能的重要前提条件。在测试工作中,仪器的精确度是至关重要的,只有在精准的技术指标基础上才能够保证仪器测量效果的准确性。文章对电声器件及其测试仪进行了简述,对电声器件测试仪校准的环境要求和量化标准进行了明晰,重点对电声器件测试仪类仪器的校准方法进行了研究。以期对电声器件测试仪类仪器的校准方法进行分析和明确,促进电声器件测试工作的准确性与科学性。     

Investigations on double-diffused MOS transistors under ESD zap conditions

In this paper we analyzed, through experiments and 2-D simulations, the behavior under high reverse voltages of a double-diffused MOS transistor. It turned out that the drift diffusion region (resistor) between the drain contact and p-diffusion region (PI) plays an important role both in the switching on of the parasitic bipolar structure and in the failure mechanism.     

Converter circuit design, semiconductor device selection and analysis of parasitics for micropower electrostatic Generators

For various medical monitoring and sensing applications it is desirable to power the electronics by scavenging energy from any locally available source. An electrostatic motion-driven generator for low-frequency (human body) motion has been developed by the authors using microelectromechanical system technology. The prototype generates pulses of 250V on a 10-pF capacitor. This paper examines the design of a circuit and semiconductor devices to convert this energy to a low voltage. Because of the very small charge involved, the effects of leakage and parasitic stored charge are important. Converters for this application using silicon-on-insulator metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors are compared using physics-based finite-element simulation. The overall effectiveness of the generation process is shown to be composed of several terms which are functions of system parameters such as generator flight time, semiconductor device area, and circuit inductance. It is shown that device area is a compromise between leakage current, charge storage, and on-state voltage. It can, for a given generator and inductance, be optimized to provide the maximum energy yield. Parasitic series inductance is shown to be of little importance to the circuit efficiency; however, parasitic capacitance has a significant influence.     

Damage to n-MOSFETs from electrical stress Relationship to processing damage and impact on device reliability

The study reported herein examines and compares damage to n-channel and p-channel metal-oxide-silicon field-effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c.) electrical stresses as well as the relationship of this damage to plasma processing damage in MOSFETs. The lightly-doped drain (LDD) MOSFETs used are of 0.5 μm channel length and with a 90 Å thick thermally grown gate oxide fabricated using a full flow CMOS process up to and including metal-1 processes and post-metallization annealing (PMA). The damage to MOSFETs is assessed using transistor parameter characterization and charge-to-breakdown measurements on the gate oxide. It is found that manifestations of d.c. stress-induced damage and a.c. stress-induced damage to transistors are fairly similar in that both forms of damage are passivated by PMA and are reactivated by a subsequent d.c. electrical stress. However, a.c. stress-induced damage is observed to occur at much lower electric fields across the gate oxide than those necessary for d.c. stress-induced damage to be significant. This is attributed to a.c. currents, caused by carrier hopping, occurring at relatively low electric fields. One implication of our results is that plasma-charging damage, often attributed to d.c. electrical stress alone, may comprise an a.c. electrical stress component too.     

基于失效特征的静电损伤分析研究

静电放电损伤失效分析是电子制造企业分析产品质量问题和提高产品质量可靠性的难点和关键技术之一。总结梳理生产制造过程中常见的静电源和释放通路,研究元器件静电放电损伤的敏感结构,研究静电放电损伤的失效机理及其典型形貌特征,探讨静电损伤(ESD)、过电损伤(EOS)和缺陷诱发失效的鉴别方法。最后将这些方法应用在具体的失效案例中,为企业开展静电放电失效分析工作提供一种有效的鉴别分析方法。     

基于FPGA的斜面冲击机末速度测试方案

为了评定运输包装件在受到水平冲击时的耐冲击强度和包装对内装物的保护能力,本文作者广泛研究的基础上基础上特别提出了一种基于FPGA的斜面冲击机末速度测试方案,经过作者实际测试表明此设计方案具有一定的实用性,达到了预期的结果,并且具有较高的灵活性,可靠性及稳定性,且价格低廉,有很大的实用价值和推广意义.     

A step by step methodology to analyze the IGBT failure mechanisms under short circuit and turn-off inductive conditions using 2D physically based device simulation

A systematic methodology is developed in order to clarify the punch through trench insulated gate bipolar transistor (T-IGBT) failure mechanisms which can occur under extreme operating conditions such as short circuit and clamped inductive switching. By considering a 2D dimensional physically based device simulation, and by analyzing some T-IGBT physical parameters, it is possible to identify if the failure mechanism is due to a breakdown, a latchup or a thermal runaway phenomenon.     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).     

Trench IGBT failure mechanisms evolution with temperature and gate resistance under various short-circuit conditions

Two extreme configurations under short-circuit conditions leading to the punch through trench IGBT failure under the effect of the temperature and the gate resistance have been studied. By analyzing internal physical parameters, it was highlighted that the elevation of the temperature causes an acceleration of the failure which is due to a thermal runaway phenomenon, whereas the influence of the gate resistance on the failure evolution is minimal.     

Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-/spl mu/m CMOS technology.     

Characterization of human metal ESD reference discharge event and correlation of generator parameters to failure levels-part II: correlation of generator parameters to failure levels

Most electrostatic discharge (ESD) generators are built in accordance with the IEC 61000-4-2 specifications. It is shown, that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprised of fast CMOS devices, while rise time and derivative of the discharge current did not correlate well. The electric parameters of typical ESD generators and ESD generators that have been modified to reflect the current and field parameters of the human metal reference event are compared and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of the first paper, of this two-paper series, are discussed with respect to reproducibility and test severity.     

Android移动设备数据加密机制

数据加密是企业级移动设备重要的功能,防止数据被未经授权的用户或应用程序所访问。谷歌从Android3.0开始提供磁盘加密解决方案。但它只对内部存储设备进行加密。本文基于eCryptFS方法提出了对Android系统内部和外部存储设备都进行数据加密的整体方案,同时也提供了对Android应用程序级的数据加密方法,提升了Android移动设备的安全性。     

浅谈空调控制器常见ESD故障现象及改善方法

本文基于VW ESD(Electrostatic Discharge 静电放电)标准,探讨空调控制器面板的零部件层面ESD测试方法,故障现象以及常用改善方法。主要内容包括空调控制面板的介绍,VW的零部件层面ESD要求以及测试大纲,以及空调面板在做ESD过程中常见的故障现象以及改善方法。     

Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide

Common ESD protection devices have a snapback characteristic similar to a silicon-control rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. In this work, it is demonstrated that the defect generation mechanism in oxide during electrical stress remains unchanged in the sub-nanosecond stress regime. As a result, the voltage transient can create far more defects in the gate oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.