Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such “compliant interconnects” are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100- $mu{hbox {m}}$ pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of $sim$ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.      

Mapping the failure envelope of board-level solder joints

Single solder interconnects were subjected to a series of combined tension-shear and compression-shear tests to determine their failure load. The failure envelope of these interconnects was obtained by plotting the normal component against the shear component of the failure load. The interconnect failure force map was found to be elliptical like the failure envelopes of many materials. The failure map can be described by a simple mathematical expression to give a simple force-based criterion for combine loading of solder joints. Post mortem analyses were conducted on the solder joint specimens to identify the failure mechanisms associated with various segments of the failure map. Computational simulations of actual board tests show that the failure map obtained for joint tests provides good predictions of board-level interconnect failures and hence suggest that such failure maps are useful in the design and analysis of board assemblies subjected to mechanical loads. The industry could adopt the methodology to obtain failure envelopes for solder joints of different alloys, bump size and reflow profiles which they could later use to aid in board-level and system-level designs of their products for mechanical reliability.     

Microprocessor and LSI Microcircuit Reliability-Prediction Model

This paper discusses the development of an improved failure-rate prediction method which can be used to assess the reliability of complex and new-technology microcircuits, especially memories, microprocessors, and their support devices. The prediction models are similar to those presented in MIL-HDBK-217C with several modifications to reflect the variation of reliability sensitive parameters and to discriminate against the device design and usage attributes which contribute to known failure mechanisms. A comparison of the failure rate predictions calculated using MIL-HDBK-217C and the actual failure rates for LSI random logic and memory devices did not indicate a reasonable correlation. An analysis of the 217C models revealed that the lack of correlation was attributable to the generic consolidation of model parameters, which ultimately reduced model sensitivity to several critical reliability factors. The model accuracy was greatly improved, without substantially increasing model complexity, by separating some generic parameters into sets of more detailed parameters. The major model revisions included: ? Complexity factors oriented toward major device function and technology categories ? Development of temperature factors for each device technology, in both hermetic and nonhermetic packages ? Introduction of an additive package failure-rate factor based upon package type and number of functional pins ? Introduction of a voltage derating stress factor for CMOS devices with maximum recommended operating supply voltage greater than 12 volts ? Introduction of a ROM and PROM programming technique factor to reflect the influence of the programming mechanism used in these devices.     

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

Some reliability considerations pertaining to LSI technology

This paper discusses the trends that have developed in LSI, and the requirements for refinements in process technology, closer process control, and improvements in design that are considered to be essential for the full realization of high LSI reliability. Particular attention is paid to advanced multilevel-structure processing and to the use of specially designed test vehicles for purposes of process improvement and process control.     

Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.     

A novel accelerated test technique for assessment of mechanical reliability of solder interconnects

New generations of lead-free solder interconnects are widely used in consumer electronics. Reliability of the devices which are subjected to rough handling, depends on the fracture resistance of the solder interconnects to shock and mechanical loading. The conventional reliability testing procedures are reported to be expensive and time consuming. Thus alternative tests and evaluation methods for reliability assessment of solder joints are required. In this study a new method for quality assessment of solder interconnects under high strain vibrational shear loading is presented using an ultrasonic fatigue testing system in combination with a special experimental set-up. Using this technique lifetime curves for solder ball bonds of two different Sn–Ag–Cu lead-free alloys were obtained. Failure mechanisms of the solder ball bonds were studied using SEM methods and the reliability curves were discussed with regard to the failure modes and the composition of the lead-free alloys. The applicability of the proposed method is discussed with regard to the literature data.     

随机工艺变化下互连线ABCD参数建模与仿真

集成电路的不断发展使得互连线的随机工艺变化问题已经成为影响集成电路设计与制造的重要因素。基于电报方程建立了工艺变化下互连线的分布参数随机模型,推导出互连线ABCD参数满足的随机微分方程组,并提出了基于蒙特卡洛法的互连线ABCD参数统计分析方法,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出了最差情况估计。实验结果表明所提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估。     

Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies

An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (DeltaT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions.     

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this work we present a low-power hybrid fault tolerant architecture for reliability improvement of pipelined microprocessors by protecting their combinational logic parts. The architecture can handle a broad spectrum of faults with little impact on performance by combining different types of redundancies. Moreover, it addresses the problem of error propagation in nonlinear pipelines and error detection in pipeline stages with memory interfaces. Our case-study implementation of a fault tolerant MIPS microprocessor highlights four main advantages of the proposed solution. It offers (i) 11.6 % power saving, (ii) improved transient error detection capability, (iii) lifetime reliability improvement, and (iv) more effective fault accumulation effect handling, in comparison with TMR architectures. We also present a gate-level fault-injection framework that offers high fidelity to model physical defects and transient faults.     

Obtaining FPGA soft error rate in high performance information systems

Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations since the majority of chip real estate is dedicated to memory bits, configuration bits, and user bits. Moreover, Single Event Upsets (SEUs) in the configuration bits of SRAM-based FPGAs result in permanent errors in the mapped design.FPGAs are widely used in the implementation of high performance information systems. Since the reliability requirements of these high performance information sub-systems are very stringent, the reliability of the FPGA chips used in the design of such systems plays a critical role in the overall system reliability. In this paper, we compare and validate the soft error rate of FPGA-based designs used in the Logical Unit Module board of a commercial information system with the field error rates obtained from actual field failure data. This comparison confirms that our analytical tool is very accurate (there is an 81% overlap in FIT rate range obtained with our analytical modeling framework and the field failure data studied). It can be used for identifying vulnerable modules within the FPGA for cost-effective reliability improvement.     

An ISDN Subscriber Loop Transmission System Based on Echo Cancellation Technique

This paper proposes an ISDN subscriber loop transmission system based on an echo cancellation technique which fully supports the CCITT recommended basic interface for ISDN, i.e.,B + B + Dover metallic cables. System design considerations of cable loss, crosstalk, impulsive noise, and system requirements such as power feeding on a caLl-by-call basis are discussed, and a transmission system is proposed. The proposed system is characterized by the use of a new line code, named "modified biphase code." The use of this code with fixed line loss equalization and coherent detection achieves circuit simplification. A special adaptation algorithm is incorporated with the echo canceller that significantly reduces convergence time. Experimental results show satisfactory performance with respect to the residual echo and the bit error rate. Since the system requires only a simple nonadaptive circuit for analog portion, it is suitable for LSI implementation.     

Quantitative evaluation of bending reliability for a flexible near-field communication tag

Flexible electronic devices under repetitive use inevitably entail damage accumulation that can cause failures in the components and interconnects. The main aim of this study involves proposing test procedures and corresponding testers that can be used to systematically evaluate the bending reliability of flexible electronic devices. In contrast to conventional bending test techniques based on a collapsing radius method, in the present study, the flexible devices were wrapped onto a roller to ensure a constant strain. An example of a near-field communication tag for smart phones was examined to verify the proposed test methods and testers. The results indicated that the critical curvature for cyclic failure was significantly lower than the static critical curvature. Curvature-life diagrams as evaluated by the proposed test method revealed that bending radius and alignment methods significantly affected the reliability of the tags. Thus, the curvature-life diagrams can be used to design a roller radius based on a predefined product life.     

A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects

During back-end manufacturing process of IC, intervention of spot defects induces extra and missing material of interconnects causing circuit failures. Interconnect narrowing occurs when spot defects induce interconnects missing material without resulting in a complete cut. The narrow sites of defective interconnects favor electromigration that makes narrow interconnects more likely to induce a chip failure than regular interconnects. In this paper, an innovative layout sensitivity model accounting for “narrow” defects is derived. The paper also pioneers estimation of the probability of narrow interconnects in the die. The layout sensitivity model for narrow interconnects is tested and compared to actual and simulated data. Our layout sensitivity model predicts the probability of narrowing with 3.1% error, on average. The model is then combined with electromigration constraints to predict mean-time-to-failure of chips manufactured in future technologies down to 32 nm node. The paper concludes with some other possible applications of the narrow interconnect predictive model.

Aluminum metallization—Advantages and limitations for integrated circuit applications

The advantages and limitations of aluminum metallization are reviewed and compared with other systems used for integrated circuits. Metallization system properties of particular importance are summarized, including initial physical and chemical properties of the system which define potential performance and reliability considerations. The special requirements for MOS arrays and for multilevel-metallized integrated circuits are described. Recently available knowledge of aluminum metallization process technology and of metallization-related failure mechanisms is reviewed, and new results of experimental studies are presented. It is concluded that aluminum will continue to be the most widely used metallization material, not only for single-level metallized integrated circuits, but also for multilevel LSI arrays.     

Random vibration analysis of 3-Arc-Fan compliant interconnects

Microelectronic packaging compliant interconnects offer increased reliability when compared to traditional rigid solder ball interconnects. These interconnects are subject to various forms of mechanical damage including thermal cycle fatigue, drop impact shock, and vibration environments that often lead to mechanical or electrical failure. Second-level compliant interconnects seek to alleviate this issue by decoupling the substrate and board, facilitating independent deformation while experiencing lower stresses and strains. In order to develop compliant interconnects as an effective alternative to rigid solder balls, various design optimization, thermal cycling test, and drop impact studies have been performed. However, the area of vibration characterization and analysis is lacking for microelectronic packaging and nonexistent for compliant interconnects. Therefore, this paper will present a complete vibration analysis of a particular multi-path compliant interconnect design, the 3-Arc-Fan compliant interconnect. This design features three electroplated copper arcuate beams that provide a spring-like effect to increase compliance and mechanical reliability. Experimental vibration characterization was performed and used to validate the simulation model. Following which a random vibration analysis method wais established, and the samples were tested at various conditions. Finally, both experimental and simulation results were integrated to develop a preliminary fatigue life prediction model to demonstrate the increased reliability.     

IC中多余物缺陷对信号串扰的定量研究

该文研究了铜互连线中的多余物缺陷对两根相邻的互连线间信号的串扰,提出了互连线之间的多余物缺陷和互连线之间的互容、互感模型,用于定量的计算缺陷对串扰的影响。提出了把缺陷部分单独看作一段RLC电路模型,通过提出的模型研究了不同互连线参数条件下的信号串扰,主要研究了铜互连线的远端串扰和近端串扰,论文最后提出了一些改进串扰的建议。实验结果证明该文提出的信号串扰模型可用于实际的电路设计中,能够对设计人员设计满足串扰要求的电路提供指导。     

具有冗余设计的铜互连线电迁移可靠性评估

铜互连的电迁移可靠性与晶粒结构、几何结构、制造工艺以及介质材料等因素有着密切的关系。分别试制了末端有一定延伸的互连线冗余结构设计的样品,以及无冗余结构的互连线样品,并对样品进行了失效加速测试。测试结果显示,采用冗余结构设计的互连线失效时间更长,具有更好的抗电迁移可靠性。对冗余结构的失效模式进行了讨论,并结合互连线的制造工艺,指出采用冗余结构设计的互连线可以在有效改善互连线的电迁移特性,而且不会引入其他影响可靠性的因素,是一种有效提高铜互连电迁移可靠性的方法。     

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments were used in the transfer function, as opposed to previous Elmore delay models which consider only one moment for RC interconnects. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using a 0.25-$mu$m CMOS technology. Simulation results show that this repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide VLSI/SoC designers with optimal design parameters, such as the type as well as the position and size of repeaters to be used for interconnect regeneration, faster than with conventional HSpice simulations.