共查询到17条相似文献,搜索用时 156 毫秒
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随着CMOS器件特征尺寸的不断缩小,绝缘栅介质层也按照等比例缩小的原则变得越来越薄,由此而产生的栅漏电流增大和可靠性降低等问题变得越来越严重。传统的SiO2栅介质材料已不能满足CMOS器件进一步缩小的需要,而利用高介电常数栅介质(高k)取代SiO2已成为必然趋势。综述了国内外对纳米尺度CMOS器件高k栅介质的等效氧化层厚度(EOT)控制技术的一些最新研究成果,并结合作者自身的工作介绍了EOT缩小的动因、方法和展望。 相似文献
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随着CMOS器件特征尺寸的不断缩小,绝缘栅介质层也按照等比例缩小的原则变得越来越薄,由此而产生的栅漏电流增大和可靠性降低等问题变得越来越严重。传统的SiO2栅介质材料已不能满足CMOS器件进一步缩小的需要,而利用高介电常数栅介质(高k)取代SiO2已成为必然趋势。而在前栅工艺下,SiO2界面层生长问题严重制约了EOT的缩小以及器件性能的提升。介绍了一种前栅工艺下的高k/金属栅结构CMOS器件EOT控制技术,并成功验证了Al元素对SiO2界面层的氧吸除作用。 相似文献
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随着45 nm和32 nm技术节点的来临,传统的SiO2作为栅介质薄膜材料的厚度需缩小到1 nm之下,材料的绝缘性、可靠性等受到了极大的挑战,已不能满足技术发展的要求.高k材料成为代替SiO2作为栅介质薄层材料的不错选择,但是大多数高k材料是离子金属氧化物,其基本物理和材料特性导致产生很多不可靠因素.从高k材料的基本物理和材料特性角度,回顾了高k材料代替SiO2用作纳米级MOS晶体管栅介质薄层时产生的主要不可靠因素及根本原因. 相似文献
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研究了淀积后退火(PDA)工艺(包括退火环境和退火温度)对高介电常数(k)HfO2栅介质MOS电容(MOSCAP)电学特性的影响.通过对比O2和N2环境中,不同退火温度下的HfO2栅介质MOSCAP的C-V曲线发现,高kHfO2栅介质在N2环境中退火时具有更大的工艺窗口.通过对HfO2栅介质MOSCAP的等效氧化层厚度(dEOT)、平带电压(Vfb)和栅极泄漏电流(Ig)等参数进一步分析发现,与O2环境相比,高kHfO2栅介质在N2环境中PDA处理时dEOT和Ig更小、Vfb相差不大,更适合纳米器件的进一步微缩.HfO2栅介质PDA处理的最佳工艺条件是在N2环境中600℃下进行.该优化条件下高kHfO2栅介质MOSCAP的dEOT=0.75 nm,Vnb=0.37 V,Ig=0.27 A/cm2,满足14或16 nm技术节点对HfO2栅介质的要求. 相似文献
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Si3N4栅MOS器件的隧穿电流模拟 总被引:2,自引:2,他引:0
随着MOS器件尺寸按比例缩小到亚100 nm时代,栅绝缘层直接隧穿(Direct Tunnel-ing,DT)电流逐渐增大.使用Si3N4材料作为栅介质,利用其介电常数高于SiO2的特性,可以在一定时期内有效地解决隧穿电流的问题.文章在二维器件模拟软件PISCES-II中首次添加了模拟高k材料MOS晶体管的器件模型,并对SiO2和Si3N4栅MOS晶体管的器件特性进行了模拟比较. 相似文献
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《Microelectronic Engineering》2007,84(9-10):1902-1905
High dielectric constant (high-k) materials, as a replacement for conventional gate dielectrics, have been proposed to overcome the problem of excessive gate leakage current. HfSiON is a potential high-k gate dielectric material, but the value of its dielectric constant is considered a little too low. In this work, we incorporate Ta into HfSiON to form a HfTaSiON gate dielectric. The influences of different Hf contents in HfTaSiON and various post deposition anneal (PDA) treatments were studied in detail. Experimental results show thatimprovements on the material and electrical properties of metal-oxide-semiconductor (MOS) devices such as crystallization temperature, interface quality between high-k dielectric/Si, hysteresis, stress-induced leakage current (SILC) and interface trap density (Dit) are achieved with incorporating a suitable amount of Hf in HfTaSiON high-k gate dielectric 相似文献
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The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2. 相似文献
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Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one... 相似文献
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Yu-Sheng Lin Chia-Hong Lin Kuo J.B. Ke-Wei Su 《Electron Devices, IEEE Transactions on》2006,53(6):1373-1378
This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step C/sub S(D)G//C/sub GS/ versus V/sub G/ curve could be identified for the device with the 1.5-nm HfO/sub 2/ gate dielectric due to the vertical and fringing displacement effects. 相似文献
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The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-κ dielectrics differ appreciably from their values on SiO2 or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO2, Si3N4, ZrO2, and HfO 2 are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-κ gate dielectrics 相似文献
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Jong Jin Lee Xuguang Wang Weiping Bai Nan Lu Dim-Lee Kwong 《Electron Devices, IEEE Transactions on》2003,50(10):2067-2072
In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles. 相似文献