A 14-b, 100-MS/s CMOS DAC designed for spectral performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm ² of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed     

A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite asymmetric digital subscriber line (ADSL) transmission is described. The transmit channel consists of application-dependent digital filters, a 14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter, and a programmable attenuator. Due to extensive on-chip digital signal processing, the codec complies with the ADSL transmit power spectral density standards without external filtering. The receive channel contains -17.5 to 33.5 dB of programmable gain staggered strategically across three stages, a 138-kHz analog low-pass filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. The receive channel has a wide input range that can accommodate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm² and dissipates 450 mW from a 3.3-V supply     

A high-linearity 50-Ω CMOS differential driver for ISDNapplications

A CMOS differential line-driver amplifier that uses positive feedback in the input stage to give transconductance multiplication and pole-zero doublet insertion is reported. The gain-bandwidth product at 60 kHz is 30 MHz and the unity-gain frequency is 2.7 MHz. The circuit operates from a single 5-V power supply and can achieve a total harmonic distortion (THD) of -78 dB for a 6-V_pp differential output signal at 40 kHz and for a load of 100 Ω and/or 150 pF. For the same measuring condition but with a load of 50 Ω and/or 150 pF, the THD is -73 dB. A power supply rejection of more than 76 dB up to 150 kHz was obtained. The chip occupies an area of 1200 mil² in a 1.5-μm CMOS technology and dissipates 20 mW     

一种高性能多位量化Σ-Δ调制器的设计

实现了一种适用于信号检测的低功耗Σ-Δ调制器。调制器采用2阶3位量化器结构,并使用数据加权平均算法降低多位DAC产生的非线性。调制器采用TSMC 0.18μm混合信号CMOS工艺实现。该调制器工作于1.8V电源电压,在50kHz信号带宽和12.8MHz采样频率下,整体功耗为3mW,整体版图尺寸为1.25mm×1.15mm。后仿真结果显示,在电容随机失配5‰的情况下,该调制器可以达到91.4dB的信噪失真比(SNDR)和93.6dB的动态范围(DR)。     

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18 μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01 pV s. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33 LSB and a differential nonlinearity (DNL) of 0.14 LSB. The DAC can achieve a maximum measured SFDR of 65.19 dB for 97.50 kHz signal at a sampling rate of 100 MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07 MHz signal the measured SFDR is 56.84 dB at 100 MSPS sampling rate. At 50 MSPS sampling frequency and 146 kHz signal the SFDR of the DAC is 65.90 dB. The measured SFDR at 538 kHz signal is 63.62 dB for a sampling rate of 50 MSPS. Measured third order intermodulation distortion of the DAC is 58.55 dB, for a dual tone test with 1.03 MHz and 1.51 MHz signals at 50 MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06 MHz signal and 100 MSPS sampling frequency, the power dissipation of the DAC is 20.74 mW with 1.8 V supply.     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration

In this paper, a novel calibration method for high-accuracy current-steering DACs is presented. Different from traditional calibration methods which achieves the calibration by adjusting the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly reduced. The 14-bit DAC has been implemented in a standard 1P6M 0.18-mum CMOS technology. The core area of the chip is around 3 mm², among which the area of the current-source block is only 0.28 mm². The measured SFDR is 81.5 dB at 1 MHz signal frequency and 100 MHz sampling frequency. For 2 MHz signal frequency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.     

一种低功耗嵌入式14位400MHz数模转换器

设计了一个14位刷新频率达400MHz,用于高速频率合成器的低功耗嵌入式数模转换器。该数模转换器采用5+4+5分段式编码结构,其电流源控制开关输出驱动级采用归零编码以提高DAC动态特性。该数模转换器核采用0.18μm1P6M混合信号CMOS工艺实现,整个模块面积仅为1.1mm×0.87mm。测试结果表明,该DAC模块的微分非线性误差是-0.9～+0.5LSB,积分非线性误差是-1.4～+1.3LSB,在400MHz工作频率下,输出信号频率为80MHz时的无杂散动态范围为76.47dB,并且功耗仅为107.2mW。     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

一种12位50MS/s CMOS流水线A/D转换器

采用TSMC 0.18μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器（ADC）。为了减小失真和降低功耗,该ADC利用余量增益放大电路（MDAC）内建的采样保持功能,去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性。使用Cadence Spectre对电路进行仿真。结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB。当输入频率为50 MHz的信号时,SFDR依然有80.51 dB。使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW。     

A wideband CMOS sigma-delta modulator with incremental dataweighted averaging

A low-complexity high-speed circuit is proposed for the implementation of an incremental data weighted averaging (IDWA) technique used for reducing digital-to-analog converter (DAC) noise due to component mismatches. IDWA can achieve very good performance even when it is used with a low oversampling ratio (OSR), which reduces demands on circuit speed and power consumption. Therefore, the IDWA is highly suitable for wideband, low-power and small-area sigma-delta modulator (SDM) implementation. Incorporating the IDWA technique, a fourth-order feedforward (FF) SDM with an OSR of 12 and a 4-bit internal quantizer is implemented with a 2.5-V 0.25-μm CMOS process. Measurement results show that the SDM operating from a 2.5-V supply voltage can achieve respective dynamic ranges (DRs) of 84/80 dB and spurious-free dynamic ranges (SFDRs) of 90/85 dB with signal bandwidths of 1.25/2 MHz at sampling frequencies of 30/48 MHz. The power dissipation is less than 105 mW and the active area is 2.6 mm². Wider bandwidth, lower OSR, less power, and lower supply voltage are achieved compared with two recently published 3.3-V/3-V CMOS wideband SDMs with comparable SNDR performance     

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-mum CMOS process. Its power dissipation is 4.64 mW from a supply voltage of 1.8 V. This active area occupies 1.2 times 0.7 mm². The measured signal-to-noise-distortion ratio achieves 44.2 dB at an input frequency of 10 MHz. The integral nonlinearity is less than plusmn1.07 LSB, and the differential nonlinearity is less than plusmn0.72 LSB. This time-domain ADC achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s.     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

A high resolution multibit sigma-delta modulator with individuallevel averaging

A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 μm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 kHz baseband. No tone is observed in the baseband as the amplitude of a 10 kHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply     

一种带可配置插值滤波器的14-Bit 1-GS/s 数模转换器

A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented.It features a selectable interpolation rate(2x/4x/8x) with a programmable interpolation filter.To improve the high-frequency performance,a "fast switching" technique that adds additional biasing to the current-switch is adopted.The datadependent clock loading effect is also minimized with an improved switch control by using a double latch.This DAC is implemented in 65 nra CMOS technology with an active area of 1.56 mm~2.The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal,respectively.     

A low-power stereo 16-bit CMOS D/A converter for digital audio

A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2-μm CMOS technology is used and the active chip area is 5 mm²      

A digital background calibration technique for time-interleavedanalog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 μm CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm², and the power dissipation is 565 mW from a 5 V supply     

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/sADC array in 1.2-μm CMOS

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-μm CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm² and the core of the parallel ADC array occupies an area of 2.7×3.3 mm². The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.