A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process

A 30 dBm ultra-low insertion loss CMOS transmit-receive switch fully integrated with an 802.11b/g/n transceiver front-end is demonstrated. The switch achieves an insertion loss of 0.4 dB in transmit mode and 0.1 dB in receive mode. The entire receiver chain from antenna to baseband output achieves a measured noise figure of 3.6 dB at 2.4 GHz. The switch has a P_1dB greater than 30 dBm by employing a substrate isolation technique without using deep n-well technology. The switch employs a 1.2 V supply and occupies 0.02 mm² of die area.     

A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems

This paper presents an RF receiver front-end for MB-OFDM-based ultra-wideband (UWB) systems. The receiver occupies only 0.35 mm² in a 0.18 mum CMOS process and consists of a low-noise amplifier, downconverter and a bandpass filter. There are no on-chip inductors and the receiver requires no off-chip matching components. The measured receiver gain is 21 dB, noise figure is less than 6.6 dB, input IIP₃ is -5.6 dBm, and the receiver consumes 19.5 mA from a 2.3 V supply. The receiver covers all the MB-OFDM bands from 3.1 to 8 GHz     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.     

1.2V and 8.6mW CMOS differential receiver front-end with 24 dB gain and -11dBm IRCP

A 60 GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24 dB without buffer amplifier), high linearity (-11 dBm input referred P_{1 dB} compression point, or IRCP), low power dissipation (4.3 mW/arm) and small die area (0.022 mm²)     

5-GHz CMOS radio transceiver front-end chipset

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-μm CMOS technology. The 4-mm² 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm² transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 90-dBΩ 10-Gb/s Optical Receiver Analog Front-End in a 0.18-μm CMOS Technology

A 10-Gb/s 90-dBOmega optical receiver analog front-end (AFE), including a transimpedance amplifier (TIA), an automatic gain control circuit, and a postamplifier (PA), is fabricated using a 0.18-mum CMOS technology. In contrast with a conventional limiting amplifier architecture, the PA is consisted of a voltage amplifier followed by a slicer. By means of the TIA and the PA codesign, the receiver front-end provides a -3-dB bandwidth of 7.86 GHz and a gain bandwidth product (GBW) of 248.5 THz-Omega. The tiny photocurrent received by the AFE is amplified to a differential voltage swing of 900 mV_pp when driving 50-Omega output loads. The measured input sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10^-12 with a 2³¹-1 pseudorandom test pattern. The optical receiver AFE dissipates a total power of 199 mW from a 1.8-V supply, among which 35 mW is consumed by the output buffer. The chip size is 1300 mumtimes1796 mum     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

A 900-MHz RF front-end with integrated discrete-time filtering

Discrete-time analog filters, rather than off-chip components, have been used to perform frequency selection and down conversion in the integrated front-end for a 900-MHz RF receiver. The first stage of frequency down conversion is implemented with a subsampling switched-capacitor sample-and-hold circuit clocked at 78 MHz. Subsequent stages of discrete-time filtering are realized using switched-capacitor biquadratic filters. An experimental prototype of the front-end had been integrated in a 0.6-μm BiCMOS technology. The circuit provides a system gain of 36 dB and 32 dB suppression of interfering channels over a 40 MHz bandwidth. Referred to the system input, the third-order intercept-point is -16 dBm, and the spot input-referred noise is -82 dBm over a 30 kHz bandwidth. The experimental circuit dissipates 90 mW from a 3.3-V supply and occupies an active area of 1.9×1.9 mm²      

2.4 GHz ISM-Band Receiver Design in a 0.18 μm Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm².     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路,该接收前端电路使用新型的带三种增益模式的LNA,并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构,使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换,优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺,所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB;在高增益模式下的双边带噪声系数为3.8dB;低增益模式下,输入三阶交调点位12.5dBm。为了获得最大的输入动态范围,低噪声放大器采用三种可调增益模式,低增益模式使用by-pass结构,大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank,滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下,功耗为33mW,芯片面积为0.66mm2。