CRT-Based High-Speed Parallel Architecture for Long BCH Encoding

Bose–Chaudhuri–Hocquenghen (BCH) error-correcting codes are now widely used in communication system and digital technology. The direct linear feedback shifted register (LFSR)-based encoding of a long BCH code suffers from the large fan-out effect of some xor gates. This makes the LFSR-based encoders of long BCH codes not keep up with the data transmission speed in some applications. The technique for eliminating the large fan-out effect by J-unfolding method and some algebraic manipulation has been proposed. In this brief, we present a Chinese remainder theorem (CRT)-based parallel architecture for long BCH encoding. Our novel technique can be used to eliminate the fan-out bottleneck. The only restriction on the speed of long BCH encoding of our CRT-based architecture is $log_{2}N$, where $N$ is the length of the BCH code.      

基于DSP的高频链并联逆变器的软开关技术

高频链并联逆变器是现代电力电子研究的一个热点.逆变器作为高频链并联系统的核心部分,实现逆变器的软开关特性,减小开关损耗是系统研究的一个重点.本文介绍了一种基于DSP的并联高频链逆变器的软开关技术.主电路采用FB-ZVZCS(全桥零电压零电流)软开关拓扑结构,结合电压外环电流内环双闭环控制系统,实现了逆变器的软开关.采用改进的PQ控制,有效地提高了负载的均流效果.仿真波形表明该逆变器具有良好的性能.     

基于介质集成悬置槽线的差分至单端功分器北大核心CSCD

设计了一种基于介质集成悬置槽线的宽带差分至单端功分器。采用槽线与微带线耦合的差分过渡结构,实现了差分电路与单端电路的互连。在较宽的工作频率范围内实现了较好的共模噪声抑制。在10.52~15.58 GHz的频率范围内,测得差分端口处的回波损耗优于10 dB。输出端口在10.1~15 GHz的频率范围内保持15 dB以上的隔离度。差分工作模式下,功分器输出的两路信号具有幅值相等、相位相反的特点。所设计的电路基于多层板结构,将槽线及其核心电路悬置于多层板内置的腔体中,具有自封装、低辐射损耗等优势。     

一种基于并行结构的快速VQ编码算法

为提高编码速度，本文提出了一种新的快速矢量量化编码搜索算法。文中首先讨论了码书矢量平均值与失真测度之间的变化关系，并根据其结果提出基本的四分法均值排序搜索算法；然后结合并行硬件的优点，提出一种基于并行结构的四分法均值排序搜索VQ编码算法。测试结果表明，与传统的完全搜索算法及部分快速搜索算法相比，本文算法大大减少了编码时间。     

基于DSP+FPGA多通道单端/差分信号采集系统

介绍了一种基于DSP+FPGA的平台,主要利用ADS8517AD转换芯片构成的具有32路单端通道或16路差分通道的信号采集存储系统,该系统通道可以选择切换,且采样率也可以改变,具有较强的灵活性。     

Turbo高速编译码技术研究

本文提出了一种高速Turbo编译码方法。从算法改进和结构改进技术两方面进行研究,以期解决现有译码算法难以实现高速这一问题。在结构改进技术方面,采用分块思想,将分量编码器分成两块并行处理,速度提高一倍;在算法改进技术方面,一方面针对目前存在的复杂度较低、性能次优的Radix-4 Max-Log-MAP译码算法,通过尺度因子的补偿,得到了译码性能较好的SF-Max-Log-MAP算法。另一方面采用了HDA停止迭代准则,有效地减少了译码时延。     

Unfolding算法实现的高速并行CRC电路的VLSI设计

文章通过分析Unfolding算法和被广泛应用的串行CRC校验电路，提出了一种新的高速并行CRC电路，给出了推导过程，并对它的优缺点进行了讨论。     

基于多域并行编码的高速IPv6流分类

IPv6的多域流分类是高速路由器设计中的一个难点.本文提出了一种使用TCAM的高速IPv6流分类方案,其核心思想是:(1)区分IPv6包头5个域字段的不同特征,根据IPv6地址的特征及其分配信息对其进行压缩,对TCP端口域实施扩展的层次编码,根据统计数据对协议域进行压缩,最终结果是把原始域的296比特转换成280比特的查找关键字,与TCAM的表项宽度相匹配;(2)使用嵌入SSRAM表查找技术,对5个域并行进行独立编码,消除瓶颈编码环节,达到线速处理要求;(3)分类规则数据库按照本文预设计的编码方式存储在TCAM中,使用流水线技术让域的编码操作和查找操作并行执行,每个TCAM访存周期完成一次查找操作.同时,为解决范围匹配问题,本文设计了一种预定义位宽的动态范围编码算法,既节省了TCAM的存储空间,又提高了硬件规则库的更新速度.分析和仿真表明,当路由查找和流分类共用一个TCAM时,使用较低的工作频率(66MHz),流分类和路由查找速度均可达到22Mpps,满足高速OC-192接口的线速查找与流分类要求.     

基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

基于AVS+实时编码的多核并行视频编码算法

面向3D高清的国家广电行业标准AVS+较大地提高了编码效率,但也增加了编码复杂度,并行编码技术是解决高复杂度编码器的有效方法。该文改变了传统视频编码的反馈环,提出一种新的视频并行编码框架,有效地实现了编码的并行化;并将该框架应用于AVS+实时编码器中,实现了一种基于AVS+实时编码的并行算法。实验结果表明,该算法充分发挥多核处理器的运算能力,在编码性能损失极小,编码延迟可控的条件下极大地提高了视频编码速率。     

Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends

Single-ended and differential phased array front-ends are developed for Ka-band applications using a 0.12 mum SiGe BiCMOS process. The phase shifters are based on CMOS switched delay networks and have 22.5deg phase resolution and <4deg rms phase error at 35 GHz, and can handle +10 dBm of RF power (P_1dB) with a 3rd order intermodulation intercept point (IIP3) of +21 dBm. For the single-ended design, a SiGe low noise amplifier is placed before the CMOS phase shifter, and the LNA/phase shifter results in 11 plusmn 1.5 dB gain and <3.4 dB of noise figure (NF), for a total power consumption of only 11 mW. For the differential front-end, a variable gain LNA is also developed and shows 9-20 dB gain and <1deg rms phase imbalance between the eight different gain states. The differential variable gain LNA/phase shifter consumes 33 mW, and results in 10 + 1.3 dB gain and 3.8 dB of NF. The gain variation is reduced to 9.1 plusmn 0.45 dB with the variable gain function applied. The single-ended and differential front-ends occupy a small chip area, with a size of 350 times 800 mum² and 350 times 950 mum2, respectively, excluding pads. These chips are competitive with GaAs and InP designs, and are building blocks for low-cost millimeter-wave phased array front-ends based on silicon technology.     

A Novel Dual-Output CCII-Based Single-Ended to Differential Converter

In this paper a novel single-ended to differential converter topology, based on second generation current conveyors (CCIIs) is proposed. The converter architecture is very simple, being formed by a dual output current-conveyor (DOCCII) and three resistances which fix the gain of the circuit independently from the active block. Also the DOCCII topology is original, having the particular feature that output signals show a very little phase shifting between the two high impedance current outputs. The circuit has been implemented in a standard CMOS technology (AMS 0.35 m), using a supply voltage of ± 0.75 V. Theoretical values, circuit simulations and post-layout simulations are also shown and their good agreement confirms the validity of the presented idea.     

Wideband LNA Compatible for Differential and Single-Ended Inputs

This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 $mu{rm m}$ CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, ${+ 1}~{rm dBm}$ IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, ${- 0.5}~{rm dBm}$ IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 ${rm mm}^{2}$.      

一种基于差动放大器的超高速脉宽调整电路

设计了一种用于超高速A/D转换器的脉宽调整电路。以基准输出电压为参照,利用差动放大器输出控制时钟输出占空比,最高可工作在1.7 GHz时钟频率下,锁定精度为50%±1%;拥有20%～80%占空比输入,且能很好地抑制时钟抖动。电路采用0.18μm工艺制作,芯片面积为0.3 mm×0.1 mm,在1.9 V电源电压下,功耗小于40 mW。     

基于ADSP-TS101S的多片DSP并行软件设计

合成孔径雷达(SAR)实时成像处理是一种典型的流水线结构,要分为很多步骤分开进行处理,并且数据量大,算法复杂.根据这些特点,我们基于ADSP-TS101S芯片,利用其链路口进行点对点通信,设计了松耦合结构通用多DSP并行信号处理板,以进行雷达实时成像处理.基于此板,我们对松耦合多片DSP的互联拓扑结构及如何利用乒乓原则增加并行度进行了介绍,并对此种结构多片DSP平台进行并行软件设计的基本方法进行了研究.最后,举例说明,对SAR处理中常用的大点数FFT算法,进行了具体实现.实践证明,利用这些方法进行多DSP并行软件设计既简洁又高效.     

用于单电源ADC的直流耦合单端到差分缓冲器

给出了单电源ADC的直流耦合单端到差分缓冲器电路.     

基于ADSP21160的高速并行信号处理板设计

利用4片ADSP2l160处理器设计雷达高速并行信号处理板，整板的峰值运算能力达2400MFLOPS，板间数据吞吐量达1280MBytes／s，基于该信号处理板易于构成完整的高性能并行信号处理系统。运用高速电路设计方法设计电路，进行了信号完整性分析和仿真。     

High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost     

A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-mum-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. An ultralow vertical fixed pattern noise of 0.1 e_rms ^- is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus). The implemented CIS with 0.18-mum technology operates at 390 frames/s and has 7.07-V/lx middots sensitivity, 61- muV/e^- conversion gain, 4.9-e_rms ^- read noise, and less than 0.4 LSB differential nonlinearity.