Optimization of low-noise GaAs MESFET's

This paper presents a device design which is an effective way of reconciling the two conflicting requirements for low-noise GaAs MESFET's. Decreasing the effective value of gate length can be achieved, without penalty of increased gate metallization resistance, by the virtue of a proper gate-recess structure. This effect can be explained by the "effective gate length" concept. The pertinent fabrication techniques and the optimal noise-figure expression are given for an optimized structure with illustrated examples.     

Deep-level and profile effects upon low-noise ion-implanted GaAs MESFET's

The noise and RF performance of recessed-gate GaAs ion-implanted MESFET's as a function of various doping profiles has been theoretically investigated. The effects of implant energy and dose as well as varying deep-level concentration are included, Degradation of device performance with increasing deep-level concentration is predicted and the responsible physical mechanisms revealed. Also, an optimum gate recess depth is shown to exist. The study has indicated a number of design rules for the fabrication of optimized low-noise ion-implanted MESFET's.     

Electron-beam fabrication of GaAs low-noise MESFET's using a new trilayer resist technique

A LO/HI/LO resist system has been developed to produce sub-half-micrometer T-shaped cross section metal lines using e-beam lithography. The system provides T-shaped resist cavities with undercut profiles. T-shaped metal lines as narrow as 0.15 µm have been produced. GaAs MESFET's with 0.25-µm T-shaped Ti/Pt/Au gates have also been fabricated on MBE wafers using this resist technique. Measured end-to, end 0.25-µm gate resistance was 80 ω/mm, dc transconductance gmas high as 300 mS/mm was observed. At 18 GHz, a noise figure as low as 1.4 dB with an associated gain of 7.9 dB has also been measured. This is the lowest noise figure ever reported for conventional GaAs MESFET's at this frequency. These superior results are mainly attributed to the high-quality MBE material and the advanced T-gate fabrication technique employing e-beam lithography.     

Monolithic integration of surge protection diodes into low-noise GaAs MESFET's

For use in practical equipment, GaAs MESFET's need Schottky gates with high energy tolerance against electrostatic discharge. This paper describes the design and fabrication technology related to the monolithic integration of protective diodes into low-noise GaAs MESFET's. A new diode structure, the grooved sidewall junction diode (GSJD), is proposed which is well suited for suppressing deterioration of the FET's RF performance. The GSJD was successfully integrated into the dual-gate low-noise GaAs FET for use in a UHF TV tuner. High energy tolerance of 50 erg was obtained in the device with a noise figure of 1.2 dB at 1 GHz.     

GaAs dual-gate MESFET's

Performance of GaAs dual-gate MESFET, including high-frequency noise behavior, was analyzed on the basis of Statz's model. Under the design considerations developed from the analysis, fabrication and characterization of a prototype device were carried out. The present analysis was confirmed to reproduce satisfactorily the performance observed. Minimum noise figure and associated gain observed in the device with two 1-µm gates were; 1.2 dB and 16.7 dB at 4 GHz, 2.2 dB and 16.3 dB at 8 GHz, and 3.2 dB and 12.6 dB at 12 GHz, respectively. More than 35-dB gain controllability was also obtained at 8 GHz.     

High-speed integrated logic with GaAs MESFET's

The feasibility of using GaAs metal-semiconductor field-effect transistors (GaAs MESFET's) in fast switching and high-speed digital integrated circuit applications is demonstrated. GaAs MESFET's with 1-/spl mu/m gate length are shown to have a current-gain-bandwidth product f/SUB T/ equal to 15 GHz. These devices exhibit a 15 ps internal delay in a large-signal switching test. A simple logic circuit consisting of MESFET's and Schottky diodes was monolithically integrated on a semiinsulating GaAs substrate. This logic circuit exhibits a propagation delay of 60 ps with no output load, and 105 ps when its output is loaded by three similar logic gates. A useful bandwidth of approximately 3 GHz is observed.     

A distributed selector IC using GaAs MESFET's withmultilayer-interconnection structure

This paper describes novel high-speed selector circuits based on the distributed circuit approach and their circuit design methodologies. Two types of distributed selectors are designed and fabricated using 0.16 μm GaAs MESFET's with multilayer-interconnection structure. Both basically consist of eight stages of series-gated source-coupled field-effect transistor (FET) logic (SCFL) selector cell units laid out in a distributed fashion. The second circuit incorporates additional functions: a data input level shifter in each cell to make an SCFL interface for the data input and a balun for single-balance transformation of the clock input. A small-signal distributed amplifier design is extended to a large-signal distributed logic IC design, taking dynamic variations in transistor parameters into consideration. The error-free operation of both fabricated distributed selector IC's is confirmed at up to 40 Gbit/s, and the first IC still exhibited eye opening with 130 mV voltage swing of the inside measurement at 70 Gbit/s, which reaches 80% of f_T of the fabricated FET. These distributed selector IC's successfully exhibit eye opening at higher bit rates compared to the conventional lumped-element design selector     

Backgating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr²⁺and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backgating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Backdating in GaAs MESFET's

The phenomenon of backgating in GaAs depletion mode MESFET devices is investigated. The origin of this effect is electron trapping on the Cr/sup 2+/ and EL(2) levels at the semi-insulating substrate-channel region interface. A model describing backdating, based on DLTS and spectral measurements, is presented. Calculations based on this model predict that closely compensated substrate material will minimize backgating. Preliminary experimental data support this prediction.     

Buried-channel GaAs MESFET's with frequency-independent output conductance

The output conductance of GaAs MESFET's is shown to be a function of frequency and to have a well-defined temperature dependence. This behavior is in agreement with other reports of the behavior of GaAs ion-implanted MESFET's. The output conductance of buried-channel GaAs MESFET's is shown to be independent of frequency and temperature. This is an important improvement in the output characteristics with many implications for GaAs analog and digital circuits.     

GaAs MESFET's with partial p-type drain regions

The use of a localized p-type region in the drain of a GaAs MESFET has been studied. Holes injected from this p-region compensate the negative space charge region at the channel-substrate interface, minimizing undesirable substrate effects. The MESFET's fabricated with p-type drain regions (called p-FET's) exhibited I-V characteristics with less hysteresis and low light sensitivity compared to standard n-type drain MESFET's. Also, less backgating effect has been observed in these p-FET's than in standard MESFET's.     

Beyond-punchthrough current in GaAs MESFET's

In a recent letter published in this journal, Patrick et al. reported on a maximum drain voltage for pinchoff Which varied exponentially with gate length in very short-gate GaAs MESFET's. The I-V characteristics given showed that this variation is associated with beyond-punchthrough drain current. Current flowing across a depleted region is an instance of the triode mode of FET operation described by other researchers in 1966. Triode-mode theory can help in the understanding of the behavior of GaAs MESFET's near pinchoff, including the devices of Patrick et al.     

Analytical model of GaAs MESFET's

A simple analytical model of GaAs MESFET's is proposed. The model is based on the assumption that the current saturation in GaAs MESFET's is related to the stationary Gunn domain formation at the drain side of the gate rather than to a pinchoff of the conducting channel under the gate. The saturation current, channel conductance, transconductance, charge under the gate, gate-to-source and drain-togate capacitances, cutoff frequency, characteristic switching time, power-delay product, and breakdown voltage are calculated in the frame of this model. The results are verified by two-dimensional computer calculations. They agree well with the results of the computer analysis and experimental data for a 1-µm gate GaAs MESFET. It is shown that a stray gate-to-drain and gate-to-source capacitance sets up a limitation of a gate length which must be larger than or about 0.1 µm for a GaAs MESFET.     

Reliability Study of GaAs MESFET's

Failure modes have been studied phenomenologically on a small-signal GaAs MESFET with a 1mu m aluminum gate. Three major failure modes have been revealed, i.e., gradual degradation due to source and drain contact degradation, catastrophic damage due to surge pulse, and instability or reversible drift of electrical characteristics during operation. To confirm the product quality and to assure the device reliability, a quality assurance program has been designed and incorporated in a production line. A cost-effective lifetime prediction method is presented that utilizes correlations between RF parameters and dc parameters calculated using an equivalent circuit model. Mean time to failure (MTTF) value of over 10/sup 8/ h has been obtained for the GaAs MESFET for an operating channel temperature of 100/spl deg/C.     

Optical Control of GaAs MESFET's

Theoretical and experimental work for the performance of GaAs MESFET's under illumination from light of photon energy greater than the bandgap of the semiconductor is described. A simple model to estimate the effects of light on the dc and RF properties of MESFET'S is presented. Photoconductive and photovoltaic effects in the active channel and substrate are considered to predict the change in the dc equivalent circuit parameters of the FET, and from these the new Y- and S-parameters under illumination are calculated. Comparisons with the measured S-parameter's without and under illumination show very close agreement. Optical techniques can he used to control the gain of an FET amplifier and the frequency of an FET oscillator. Experimental results are presented showing that the gain of amplifiers can be varied up to around 20 dB and that the frequency of oscillators can be varied (tuning) around 10 percent when the optical absorbed power in the active region of the FET is varied by a few microwatts. When the laser beam is amplitude-modulated to a frequency close to the free-running FET oscillation frequency, optical injection locking can occur. An analytical expression to estimate the locking range is presented. This shows a fair agreement with the experiments. Some suggestions to improve the optical locking range are presented.     

Degradation mechanism of GaAs MESFET's

The degradation mechanism of X-band low-noise GaAs MESFET's is examined to obtain meaningful information on a common mode of failure. The devices tested have a half-micrometer gate (Au/ Mo) and source and drain ohmic contacts (Au/Ni/Au-Ge). Zero bias drain conductanceg_{D0}is considered as a representative parameter for degradation during aging. The major failure mode is an increase in series resistance of the ohmic contacts. The amount of degradation, decrease ing_{D0}, is proportional to the square root of aging time, and accompanied by an increase in minimum noise figureF_{min}. A degradation model based on the formation of a high-resistance layer between the ohmic metals and GaAs crystal by a diffusion reaction mechanism is proposed, resulting in excellent agreement between calculated and experimental results. Using ion-microspectroscopy analysis (IMA), diffusion of Ni into GaAs crystal is revealed. Mean time to failure (MTTF) is estimated to be 10⁷-10⁸h at channel temperature of 80°C with an increase inF_{min}of 0.5 dB as failure criterion.     

Very short gate-length GaAs MESFET's

GaAs MESFET's with gate lengths ranging from 0.36 µm down to 0.055 µm, the smallest so far reported, have been fabricated using electron-beam lithography. DC output characteristics were obtained from all of the devices tested and transconductances up to 300 mS/mm were measured. However it was observed that there is a maximum drain-source voltage that can be pinched off in these short gate devices. This voltage varies exponentially from 1 V in the 0.055-µm gate devices to 6 V in the 0.36-µm device. It is speculated that this effect is due to current injection into the buffer layer.     

Quasi-two-dimensional modeling of GaAs MESFET's

A numerical simulation of GaAs MESFET structures is presented. The approach taken in this paper combines an analytical solution with a full simulation. Poisson's equation, the current continuity equation, and an electron-temperature equation are formulated in terms of a geometry factor that defines the shape of the conducting channel in the MESFET. The transport equations are then solved in one dimension and the channel geometry factor is found analytically. This method was found to be considerably faster than full two-dimensional simulations. The model has been compared to full two-dimensional drift-diffusion and energy-momentum results to determine its validity.     

Substrate current in GaAs MESFET's

It is shown that the substrate current in GaAs MESFET's may be related to the electron injection into the substrate region adjacent to the high-field domain in the active layer. A simple one-dimensional calculation shows that the substrate current Isubis proportional toVmin{ds}max{1/2}andnmin{0}max{1/4}where Vdsis the drain-to-source voltage, n0is the doping density in the active layer. Atn_{0} = 10^{17}cm^-3andV_{ds} simeq 10V we estimateI_{sub} sim 50mA per millimeter gate in good agreement with experimental results.     

Reverse breakdown in GaAs MESFET's

A simple numerical technique for calculating reverse breakdown voltage in GaAs MESFET's is described. The breakdown voltage is determined from an integral over the ionization rate and requires only a small amount of computing time, allowing a variety of structures to be studied. The effects of a gate recess and n⁺layer, the surface potential, buried channel layers, and AlGaAs spacer layers underneath the gate are investigated.