Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Fabrication and characterization of directly-assembled ZnO nanowire field effect transistors with polymer gate dielectrics

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.     

Oxidation resistance of thin boron carbo-nitride films on Ge(100) and Ge nanowires

Chemical vapor deposition of thin (< 10 nm) films of amorphous boron carbo-nitride (BC_0.7N_0.08, or BCN) on Ge(100) and Ge nanowire (GeNW) surfaces was studied to determine the ability of BCN to prevent oxidation of Ge. X-ray photoelectron spectroscopy was used to track Ge oxidation of BCN-covered Ge(100) upon exposure to ambient, 50 °C deionized water, and a 250 °C atomic layer deposition HfO₂ process. BCN overlayers incorporate O immediately upon ambient or water exposure, but it is limited to 15% O uptake. If the BCN layer is continuous, the underlying Ge(100) surface is not oxidized despite the incorporation of O into BCN. The minimum continuous BCN film thickness that prevents Ge(100) oxidation is ~ 4 nm. Thinner films (≤ 3.2 nm) permitted Ge(100) oxidation in each of the oxidizing environments studied. GeNWs with a 5.7 nm BCN coating were resistant to oxidation for at least 5 months of ambient exposure. High resolution transmission electron microscopy images of HfO₂/BCN/Ge(100) cross-sections and BCN-coated GeNWs reveal clean, abrupt BCN-Ge(100) interfaces.     

NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors with high-k Al(2)O(3) gate layers

Electrical characteristics of NOT and NAND logic circuits fabricated using top-gate ZnO nanowire field-effect transistors (FETs) with high-k?Al(2)O(3) gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whose I(on)/I(off) ratios were as high as ～10(8) were connected in series in a single ZnO nanowire channel, sharing a common source electrode. Its voltage transfer characteristics exhibited an inverting operation and its logic swing was?98%. In addition, the characteristics of a NAND logic circuit composed of three top-gate FETs connected in series in a single nanowire channel are discussed in this paper.     

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.     

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

Abstract

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.     

Enhanced channel modulation in dual-gated silicon nanowire transistors

Dual-gated silicon nanowire (SiNW) field-effect transistors (FETs) have been fabricated by using electron-beam lithography. SiNW devices (W approximately 60 nm) exhibit an on/off current ratio greater than 10(6), which is more than 3 orders of magnitude higher than that of control devices prepared simultaneously having a large channel width (approximately 5 microm). In addition, by changing the local energy-band profile of the SiNW channel, the top gate is found to suppress ambipolar conduction effectively, which is one of the factors limiting the use of nanotube or nanowire FETs for complimentary logic applications. Two-dimensional numerical simulations show that the gate-induced electrostatic control is improved as the channel width of the FETs decreases. Therefore, enhanced channel modulations can be achieved in these dual-gated SiNW devices.     

Degradation pattern of SnO(2) nanowire field effect transistors

The degradation pattern of SnO(2) nanowire field effect transistors (FETs) was investigated by using an individual SnO(2) nanowire that was passivated in sections by either a PMMA (polymethylmethacrylate) or an Al(2)O(3) layer. The PMMA passivated section showed the best mobility performance with a significant positive shift in the threshold voltage. The distinctive two-dimensional R(s)-μ diagram based on a serial resistor connected FET model suggested that this would be a useful tool for evaluating the efficiency for post-treatments that would improve the device performance of a single nanowire transistor.     

Experimental study on the subthreshold swing of silicon nanowire transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.     

Morphology control of self-catalyzed germanium nanostructures with graphitic carbon shell

The crystalline germanium nanowires (GeNWs) with a uniform graphitic carbon shell were prepared via a conventional low-pressure chemical vapor deposition method without any external catalyst. The GeNWs grown at low temperature (Tg < 500 degrees C) have a uniform diameter with a large expect ratio of more than 10(3). With increasing the growth temperature (Tg > 500 degrees C), however, the nanowire morphology is dramatically changed into a hybrid structure where highly dense Ge nanoparticles (GeNPs) with a diameter of 5-10 nm are attached onto the Ge nanowires. The nanostructures consist of crystalline Ge-core and very thin graphitic carbon shell. The possible mechanism of anisotropic growth and the control of morphological transition from uniform nanowires to NW/NP hybrid structures are discussed and demonstrated.     

UV photoconductivity characteristics of ZnO nanowire field effect transistor treated by proton irradiation

We investigated the UV photoconductivity characteristics of ZnO nanowire field effect transistors (FETs) irradiated by proton beams. After proton beam irradiation (using a beam energy of 10 MeV and a fluence of 10¹² cm^− 2), the drain current and carrier density in the ZnO nanowire FETs decreased, and the threshold voltage shifted to the positive gate bias direction due to the creation of interface traps at the SiO₂/ZnO nanowire interface by the proton beam. The interface traps produced a higher surface barrier potential and a larger depletion region at the ZnO nanowire surface, affecting the photoconductivity and its decay time. The UV photoconductivity of the proton-irradiated ZnO nanowire FETs was higher and more prolonged than that of the pristine ZnO nanowire FETs. The results extend our understanding of the UV photoconductivity characteristics of ZnO nanowire devices and other materials when irradiated with highly energetic particles.     

Tuning the electrical performance of Ge nanowire MOSFETs by focused ion beam implantation

In this work, we demonstrate an approach to tune the electrical behavior of our Ω-gated germanium-nanowire (Ge-NW) MOSFETs by focused ion beam (FIB) implantation. For the MOSFETs, 35 nm thick Ge-NWs are covered by atomic layer deposition (ALD) of a high-κ gate dielectric. With the Ω-shaped metal gate acting as implantation mask, highly doped source/drain (S/D) contacts are formed in a self-aligned process by FIB implantation. Notably, without any dopant activation by annealing, the devices exhibit more than three orders of magnitude higher I(ON) currents, an improved I(ON)/I(OFF) ratio, a higher mobility and a reduced subthreshold slope of 140 mV/decade compared to identical Ge-NW MOSFETs without FIB implantation.     

Effects of High-κ (HfO2) Gate Dielectrics in Double-Gate and Cylindrical-Nanowire FETs Scaled to the Ultimate Technology Nodes

In this work we investigate the performance of double-gate and cylindrical nanowire FETs with high-kappa gate dielectrics at their extreme miniaturization limits. The model fully accounts for quantum electrostatics; current transport is simulated by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements for both SiO₂ and HfO₂ gate dielectrics. The on-current is simulated using both the quantum drift-diffusion model and a full-quantum transport approach based on the quantum transmitting boundary method, which assumes a purely ballistic transport. The performance comparison between SiO₂ and HfO₂ insulated-gate FETs with the same electrical oxide thickness demonstrates that the latter provides a slight degradation of the short-channel effect compared with the former but, at the same time, gives an improved on-current due to lateral capacitive-coupling effects, despite the inherent degradation of the low-field mobility     

Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics

We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW field-effect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.     

Scalable fabrication of self-aligned graphene transistors and circuits on glass

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (～20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.     

Electric Field Effect on the Magnetic Properties of III–V Ferromagnetic Semiconductor (In,Mn)As and ((Al),Ga,Mn)As

We have investigated the magnetotransport properties of field-effect transistors (FET) having a III–V ferromagnetic semiconductor channel layer. One can control not only the ferromagnetic transition temperature T _C but also the magnetization and the coercive force of (In,Mn)As channel layers isothermally and reversibly by gate electric fields. A small change of the magnetization upon application of gate electric fields is also observed in FETs with a (Ga,Mn)As channel. Results on a (Al,Ga,Mn)As channel FET are also presented.     

Improved performance of ZnO nanowire field-effect transistors via focused ion beam treatment

A seven orders of magnitude increase in the current on/off ratio of ZnO nanowire field-effect transistors (FETs) after Ga( + ) irradiation was observed. Transmission electron microscopy characterization revealed that the surface crystal quality of the ZnO nanowire was improved via the Ga( + ) treatment. The Ga( + ) irradiation efficiently reduces chemisorption effects and decreases oxygen vacancies in the surface layer. The enhanced performance of the nanowire FET was attributed to the decrease of surface trapped electrons and the decrease in carrier concentration.     

Electrical Characteristics of Hybrid Nanoparticle–Nanowire Devices

Gold nanoparticles synthesized by a colloidal method were deposited in an Al₂O₃ dielectric layer of an omega-gated single ZnO nanowire FET. These gold nanoparticles were utilized as localized trap sites. The adsorption of the gold nanoparticles on an Al₂O₃-coated ZnO nanowire was confirmed by high-resolution transmission electron microscopy. In this study, a hybrid nanoparticle-nanowire device was fabricated by conventional Si processing. Its electrical characteristics indicated that electrons in the conduction band of the ZnO nanowire can be transported to the localized trap sites by gold nanoparticles for gate voltages greater than 1 V, through the 10-nm-thick Al ₂O₃ tunneling oxide layer.