Integration of hierarchical test generation with behavioralsynthesis of controller and data path circuits

This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible     

A Generalized KYP Lemma-Based Approach for H ∞ Control of Singularly Perturbed Systems

In this paper, H _∞ control synthesis of linear time invariant singularly perturbed systems (SPS) based on a generalized KYP lemma approach is investigated. By employing a generalized KYP lemma on the low- and high-frequency domains of SPS, respectively, a slow (low-frequency) controller and a fast (high-frequency) controller are designed to stabilize the slow and fast subsystems, and also to meet the individual H _∞ performance specifications. A composite controller for the full-order SPS is constructed via the above two above well-defined lower-order problems. Moreover, the effectiveness of the proposed method is verified as compared with the traditional H _∞ design method by its application to a tracking problem of SPS and an H _∞ model matching problem for SPS.     

Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows

This paper presents a flexible controller structure for concurrent processing of memory centric coarse grain data flows. We propose a design flow based on block level pipelining where concurrency among processing blocks is fully maintained. The controller is dynamically reconfigurable to support dynamic data-flow structure changes by localizing control signals. The proposed control design method isolates controllers and processing logics such that system integration is simplified while controllers are locally configured from orthogonal global information. The controller also supports interfacing with external processors for asynchronous processing. The controller for heterogeneous processing blocks is synthesized and verified using Verilog and SystemC on FPGA. We present an example demonstrating the effectiveness of the controllers where dynamic reconfiguration of the execution is feasible.

A framework for synthesis and verification of analog systems

In this paper we present a framework for synthesis and verification of analog systems. The famework is composed of a synthesis module and a verification module. Synthesis is in the form of architectural synthesis from behavioral specifications, and verification in the form of behavioral simulation of the synthesized architectures. The synthesis and verification techniques are implemented in an object-oriented paradigm, using anopen systems approach which enables customizing the target CAD framework. An Architecture Specification Language (ASL) is defined using the C++ programming language constructs. The integrated synthesis-verification framework provides for design space exploration enabling trade-offs in architectural as well as circuit technology characteristics. This paper focuses on the framework and implementation aspects of the architectural synthesis and verification methodology.     

On-Line Monitor Design of Finite-State Machines

On-line monitoring is a useful technique for ensuring system reliability. By continuously supervising the system's operation, a wide range of problems, such as physical defects, transient faults and design errors, can be detected. A monitor M*'s behavior can be viewed as an abstraction of the target system M's behavior, and can be represented by a homomorphic mapping from M to M*. We present a systematic procedure to select homomorphisms for monitor design and measure their costs based on a behavioral fault model. Analysis of the method shows that monitors with very few states and low area can provide high fault coverage. Experimental results are presented which quantify the basic trade-off between area overhead and fault coverage. Simulation results under the industry-standard single stuck-at fault model are also reported.     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

Physical‐Aware Approaches for Speeding Up Scan Shift Operations in SoCs

System‐on‐chip (SoC) designs have a number of flip‐flops; the more flip‐flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical‐aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout‐aware flip‐flop insertion and scan shift operation–aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state‐of‐the‐art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.     

An Approach to H ∞ Control of a Class of Nonlinear Stochastic Systems

This paper studies the problems of the stochastic stabilization and H _∞ control of a class of nonlinear stochastic systems that can be represented by a stochastic heterogeneous model. Based on this model, the problem of stabilization with state feedback controller is first considered, and a new H _∞ controller design method is then developed. Synthesis of both stabilization and H _∞ controller is based on the solutions of linear matrix inequalities (LMIs). Finally, an example is given to illustrate the effectiveness of the approach proposed in this paper.     

DSSDN: Demand‐supply based load balancing in Software‐Defined Wide‐Area Networks

One of the unexplored research areas in Software Defined Networks (SDN) is load balancing of control messages (e.g. packet_in) among distributed controllers in Wide Area Networks. In SDN, on every unsuccessful match in the flow table for the incoming traffic flows, the switch sends packet_in to the controller for further action against the traffic flow. The packet_in messages are one of the major contributors of the control request (load) received by the controller. When it exceeds a certain threshold limit, the response time for the control request increases nonlinearly due to the over CPU utilization and congestion. When the controller gets overloaded, typically the OpenFlow‐enabled Devices (OFDevices) are migrated from the current controller to another under loaded controller domain. This migration might cause large degradation of end users' QoS metrics. To resolve this issue, we introduce basic demand and supply curve based DSSDN, a new load balancing method that utilizes the load factors of Software Defined Wide Area Networks controllers. This method selects the OFDevice which causes maximum load on the controller and traversing minimum users traffic through it. The Karush‐Kuhn‐Tucker conditions are employed during the optimal controller selection by the OFDevices to improve the response time effectively. During implementation, virtual threads running on the controller representing the OFDevices are used to take the optimal decision instead of actual OFDevices. The experimental results show that during migration, the DSSDN stabilizes the load hikes, improves QoS, and increase the end users' utility without much disruptions in the network state.     

Dual-band bandpass filter based on mixed electric and magnetic coupling of the hybrid quasi-lumped resonator

A novel compact dual-band bandpass filter based on mixed coupling of the hybrid quasi-lumped resonator is proposed. The filter is composed of two independent signal paths, each can generate one passband with two identical hybrid quasi-lumped resonators. The proposal combines the mixed electric and magnetic coupling technology with this novel resonator in the filter design. Analysis of the filter has been done with the equivalent circuit method. To validate the approach, a dual-band bandpass filter operating at 2.4/5.2 GHz has been fabricated. Both passbands were realised with mixed coupling. An additional transmission zero is generated at either passband. Final fabricated filter has good band skirt, low insertion loss and good out-of-band performance. Reasonable agreement is found between the calculated, simulated and measured results. The implementation area is 0.21λ_g × 0.12λ_g.     

Design and implementation of robust visual servoing control of an inverted pendulum with an FPGA-based image co-processor

This paper presents the design and implementation of robust real-time visual servoing control with an FPGA-based image co-processor for a rotary inverted pendulum. The position of the pendulum is measured with a machine vision system. The pendulum used in the proposed system is much shorter than those used in published vision-based pendulum control system studies, which makes the system more difficult to control. The image processing algorithms of the machine vision system are pipelined and implemented on a field programmable gate array (FPGA) device to meet real-time constraints. To enhance robustness to model uncertainty and to attenuate disturbance and sensor noise, the design of the stabilizing controller is formulated as a problem of the mixed H₂/H_∞ control, which is then solved using the linear matrix inequality (LMI) approach. The designed control law is implemented on a digital signal processor (DSP). The effectiveness of the controller and the FPGA-based image co-processor is verified through simulation and experimental studies. The experimental results show that the designed system can robustly control an inverted pendulum in real-time.     

Behavioral-level synthesis of heterogeneous BISR reconfigurableASIC's

In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including: (1) design for fault tolerance against permanent faults, (2) design for Improved manufacturability, and (3) design of application specific programmable processors (ASPPs)-processors designed to perform any computation from a specified set on a single implementation platform. This paper focuses on design techniques for efficient built-in self-repair (BISR), and thus directly addresses the former two applications. Previous BISR techniques have been based on replacing a failed module with a backup of the same type. We present new heterogeneous BISR methodologies which remove this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behavioral-level synthesis to explore the design space. Two behavioral synthesis techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental results verify the effectiveness of the approaches     

Time domain approach to recursive digital filter synthesis

The problem of the design of IIR digital filters, when the analog filter has been synthesized, resides in the approximation of a continuous system by means of a discrete one. We present a synthesis method which discretizes an Input-State-Output (I-S-O) model of the analog filter and is completely performed in the time domain. The basis of the method is the way in which the problem is stated, which points out the fundamental role played by the interpolator and allows an easy implementation.The main advantages of our method, with reference to traditional approaches, are:

• •- it allows direct working on continuous representations of the analog filter and the discretization does not require symbolic calculations as in approaches based on substitution techniques (for example bilinear transformation);
• •- it is completely numerical and is very simple from a computational point of view;
• •- it can be used for single and multiple input-output filters;
• •- it allows longer sampling periods using suitable interpolators.

An example is discussed which allows a comparison with the synthesis method based on bilinear transform and shows, also, that computing time may be saved as the sampling period may be traded off with the interpolator order.     

一种SD卡控制器的硬件实现

通过分析SD卡物理层规范,设计了一种采用SD总线的SD卡控制器,该控制器可以实现对于SD卡的基本控制,如:初始化SD卡、读写数据、擦除数据等操作.该控制器应用于一款采用AMBA总线的多媒体SoC芯片.该设计采用硬件描述语言(Verilog)实现,利用SYNOPSYS公司的EDA工具(VCS和DC)对该控制器进行仿真、综合,最后采用FPGA验证控制器功能正确性.本文阐述了该控制器的设计思路、模块划分以及每个模块的具体设计,最后给出仿真、综合以及FPGA验证的结果.     

基于单片机的多计算机外设共享控制器的设计与实现

为了解决多计算机外设共存的问题,通过对多计算机外设兼容设计的研究,文章提出一种基于单片机的外设共享控制器的设计的方法.该方法包含基于单片机的外设共享控制器的主要设计思路和实现方法9硬件设计采用单片机与继电器,软件采用Keil C开发.目前该方法已经投入应用,通过应用表明该设计方法方便可靠.     

High-Throughput Screening Assisted Discovery of a Stable Layered Anti-Ferromagnetic Semiconductor: CdFeP2Se6

Recent advances in 2D magnetism have heightened interest in layered magnetic materials due to their potential for spintronics. In particular, layered semiconducting antiferromagnets exhibit intriguing low-dimensional semiconducting behavior with both charge and spin as carrier controls. However, synthesis of these compounds is challenging and remains rare. Here, first-principles based high-throughput search is conducted to screen potentially stable mixed metal phosphorous trichalcogenides (MM^′P₂X₆, where M and M^′ are transition metals and X is a chalcogenide) that have a wide range of tunable bandgaps and interesting magnetic properties. Among the potential candidates, a stable semiconducting layered magnetic material, CdFeP₂Se₆, that exhibits a short-range antiferromagnetic order at T_N = 21 K with an indirect bandgap of 2.23 eV is successfully synthesized . This work suggests that high-throughput screening assisted synthesis can be an effective method for layered magnetic materials discovery.     

Platinum Lead Nanostructures: Formation,Phase Behavior,and Electrocatalytic Properties

This paper describes the synthesis and crystal phase behavior of platinum lead nanorods. Both face‐centered cubic (fcc) Pt_100?xPb_x (x < 50) and hexagonally close‐packed (hcp) Pt₅₀Pb₅₀ nanostructures are synthesized at mild reaction temperatures (180–200 °C). The crystal phase and composition of these PtPb nanorods can be controlled by changing the reaction time and temperature. A mechanism for the formation of either kinetically or thermodynamically stable PtPb nanorods is discussed. The approach developed for controlling crystal phases at fairly low temperatures can be important for the design of alloy or intermetallic nanostructures for a broader range of applications.     

Design and control of a mechanical rotary variable impedance actuator

To realize different tasks in human-robotic interaction, various mechanical variable stiffness actuators are being investigated. A mechanical-rotary impedance actuator (the MeRIA) is presented that is based on the controllable effective length of a mechanical bending bar, which can be implemented into an orthosis for future research on rehabilitation training. The actuator provides joint motion and variable stiffness, simultaneously. The control task can be decoupled to be a decentralized control structure for which the controller of the two motor power sources can be designed respectively. For the movement control-loop, a cascaded impedance controller with position-torque-velocity control-loops are designed to maintain a stable and safe working environment. Using an H_∞ loop-shaping methodology, a robust stabilization torque controller is achieved. The trade-off between the actuators performance and stability is taken into account to obtain a desired shape as a precondition of an H_∞ controller synthesis. The actuator is tested on a test bench using rapid control prototyping. A model reduction algorithm is implemented to simplify the controller, and a prefilter design reduces the control-loop overshoot, thereby improving the robust stability and tracking performance during application. Experiments show that the MeRIA meets all the requirements for a mechanical device attached to the body.