A study of the threshold voltage variation for ultra-small bulk andSOI CMOS

This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (V_TH) fluctuations. The impact of dopant-induced V_TH variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be seriously degraded as the channel length approaches 25-30 nm even if an elaborate redundancy scheme is used. For the IC-SOI FETs, instead of the dopant fluctuations, silicon thickness variation is a critical issue. However, systematic simulation results show that, by optimizing the FET design, the thickness-induced V_TH variations for both planar single gate and vertical double gate 25 mm IC-SOI FETs will be acceptable, assuming a reasonable thickness deviation range. Therefore, the IC-SOI CMOS is expected to be superior to the bulk counterpart at L=25 nm. It was also found that optimizing the back bias is necessary for suppressing the V_TH variations of the single gate IC-SOI FETs     

A 86 to 108 GHz Amplifier in 90 nm CMOS

This letter presents a CMOS amplifier with 22 GHz 3-dB bandwidth ranging from 86 to 108 GHz. The amplifier is implemented in 90 nm mixed signal/radio frequency (RF) CMOS process using three-stage cascode RF NMOS configuration. It achieves a peak gain of 17.4 dB at 91 GHz from the measured results. To our knowledge, this is the highest frequency CMOS amplifier reported to date.     

A transient analysis of latchup in bulk CMOS

This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.     

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant

Electrical and SEM analysis of gate-silicided (GS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism changes from source-to-drain filamentation to drain-to-substrate short when a p-type ESD implant (ED) is used. Simulations show that the reason for change in failure mode is the different current and temperature distribution when the device is operated in bipolar mode due to the presence of ED. The size of the drain silicide blocking can be reduced from 3 to 0.75 μm by the use of ED while keeeping the same ESD failure current with the corresponding area saving benefit. When the ED implant extends under the drain contacts, the on-resistance (Ron) of the device can be reduced by 50% with respect to a design where ED is not located under the contacts.     

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.     

Characterization of parasitic transistors to evaluate CMOS processuniformity

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed and their application to process control examined. These transistors are characterized and their extracted parameters correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors are very sensitive to changes in the process that influence the performance of MOS transistors. As a result parasitic transistors can be used in conjunction with standard MOS devices and test structures to provide a more complete picture of CMOS process variation     

Variations in performance degradation of CMOS NAND gates due to ionizing radiation

Performance degradation of operating parameters of integrated circuits has been known to increase with increasing total doses of ionizing radiation. It is the aim of this paper to demonstrate that, while these effects are cumulative, individual sub-circuits may be affected differently. To that effect, statistical samples of quad NAND gates have been irradiated to several increasing total doses and the parameter degradations of the individual gates have been compared at each dose step. The research showed that there is a similar degradation profile for gates of the same physical location but that there is a significant difference between the gates on each IC. This paper therefore presents the different parameter degradation profiles and suggests some degradation models as functions of total dose.     

一种带有25%占空比本振采用130 nmCMOS工艺应用于LTE直接变频无声表滤波器接收机设计

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.     

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

Experimental study and analysis of corner compensation structures for CMOS compatible bulk micromachining using 25 wt% TMAH

In the present work, most common compensation structures (〈1 1 0〉 squares and 〈1 0 0〉 bars) have been used for convex corner compensation with 25 wt% TMAH-water solution at 90±1 °C temperature. Etch flow morphology and self-align properties of the compensating structures have been investigated. For 25 wt% TMAH water solution {3 1 1} plane is found to be responsible for corner undercutting, which is the fast etch plane. Etch-front-attack angle is measured to be 24°. Generalized empirical formulas are also discussed for these compensation structures for TMAH-water solution. 〈1 1 0〉 square structure protects mesa and convex corner and is the most space efficient compared to other compensation structures, but unable to produce perfect convex corner as 〈1 0 0〉 bar type structures. Both the 〈1 0 0〉 bar structures provide perfect convex corners, but 〈1 0 0〉 wide bar structure is more space efficient than the 〈1 0 0〉 thin bar structure. Implications of these compensation structures with realization of accelerometer structure have also been discussed. A modified quad beam accelerometer structure has been realized with these compensation structures using 25 wt% TMAH.     

A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS

Transistors in aggressively scaled CMOS technologies have f_T greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm² active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching.     

一种500 Mbps至4 Gbps连续速率的多模式CDR电路

提出了一种连续速率的时钟数据恢复(CDR)电路,可覆盖500 Mbps到4 Gbps数据率。该CDR电路在130 nm互补金属氧化物半导体(CMOS)工艺下实现,基于相位插值(PI)原理,采用数字投票电路和相位控制逻辑替代电荷泵和模拟滤波器以方便工艺移植。为缩小片上锁相环(PLL)输出时钟频率范围,同时避免PI电路处于非线性区,该CDR电路采用多种速率模式切换的方式将采样时钟频率限定在500 MHz~1 GHz之间。PI电路为7 bit精确度,线性度良好,4 Gbps数据率时,恢复时钟的峰峰值抖动约为25.6 ps。该CDR误码率在10-10以下,可跟踪最大±976.6 ppm的数据频偏,功耗约为13.28 mW/Gbps,测试芯片大小为5 mm2,其中CDR芯核部分为0.359 mm2。     

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 ${hbox{mm}}^{2}$ and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.      

一种基于非线性补偿技术的混合模式65nm CMOS带隙基准源

通过对当前已有的两种低温漂带隙电压源进行分析和总结,提出了一种新型温度补偿技术.采用双端分段非线性补偿、对数项消除技术以及混合模式拓扑输出方式,设计了一种具有高温度稳定性的带隙电压基准源.整个电路基于65nm CMOS工艺实现,并成功应用于一种65nm CMOS触摸屏控制器中.当电源电压为2.5V时,带隙电压源的输出为949mV.当温度在-40℃～125℃范围变化时,输出电压仅变化0.44mV,温度系数约为2.87ppm/℃,非常符合高精度SoC的应用.     

Parametric study of latchup immunity of deep trench-isolated, bulk,nonepitaxial CMOS

The improvement of latchup immunity in bulk, nonepitaxial CMOS with deep trench isolation has been demonstrated using numerical simulation. Through a proper design of trench dimensions and layout, it is shown that the holding voltage can be increased to a level above the power supply voltage (3.3 V in deep-submicrometer CMOS), yielding latchup-free CMOS even for nonepitaxial substrates. The holding voltage is strongly influenced by the current flow patterns in the conductivity-modulated well and substrate regions, which are affected by trench depth, layout parameters, and the tank and p⁺/n⁺ emitter doping concentrations. The deep trench makes the current flow patterns two-dimensional, and this causes parametric dependencies that cannot be explained from simple trench-isolation techniques. Design issues that are unique to deep trench isolation have been identified     

一款基于65nm CMOS工艺的高效率50GHz 压控振荡器及其电感耦合效应的研究

A 50 GHz cross-coupled voltage controlled oscillator(VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor(CMOS) technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO’s LC tank.By optimizing the tank voltage swing and the buffer’s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW(including buffers).The VCO exhibits a phase noise of—87 dBc/Hz at 1 MHz offset,leading to a figure of merit(FoM) of-167.5 dB/Hz and a tuning range of 3.8%(from 48.98 to 50.88 GHz).     

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Classical scaling equations which estimate parameters such as circuit delay and energy per operation across technology generations have been extremely useful for predicting performance metrics as well as for comparing designs across fabrication technologies. Unfortunately in the CMOS deep-submicron era, the classical scaling equations are becoming increasingly less accurate and new practical scaling methods are needed. We curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models. While the classical scaling equations give differences as much as 83×from the predictions of PTM and ITRS models, our predictive polynomial models with table-based coefficients yield a coefficient of determination, or R², value of greater than 0.95.     

Technology Dependency of TID Response for a Custom Bandgap Voltage Reference in 65 nm to 28 nm Bulk CMOS Technologies

Total ionizing dose(TID) radiation response of the custom bandgap voltage reference(BGR)fabricated with 65 nm, 40 nm and 28 nm commercial bulk CMOS technologies is investigated. TID response is assessed employing Co-60 gamma ray source. The measurements indicate that the voltage reference is reduced by5.67% in 28 nm, 0.56% in 40 nm and increased by 1.28% in65 nm devices under irradiation up to 1.2 Mrad(Si) TID.After 48 hours of annealing, the voltage reference changes are just-1.84% in 28 nm, 0....     

A 10 bit 1 GSPS Nyquist DAC in 180 nm CMOS with high FOM

A new segmented architecture is presented to improve the dynamic and static performance of the current steering digital-to-analog converters (DACs). In the proposed architecture instead of a single binary DAC, distributed binary cells are used. So the effect of the mismatch and timing errors of the binary cells are not accumulated and are averaged out. For realization of the MSB unit cells those binary cells are reused to form the larger weighted unit cells. Realization of the MSB unit cells with smaller cells results in improved dynamic performances as the effects of gradient errors are minimized and the effects of nonlinear parasitic capacitances are reduced. The DAC has been designed in 180 nm five-metal nwell CMOS process. The simulation results show that the DAC can achieve a maximum spurious free dynamic range (SFDR) of 70.99 dB at 2.93 MHz signal for a sampling rate of 1 GSPS considering the mismatch effects. For 1 GSPS sampling rate the simulated Nyquist SFDR is >70 dB with mismatch. The simulated third order intermodulation distortion (IM3) of the DAC with mismatch effect is 71.40 dB, for a dual tone test with 491.21 and 495.12 MHz signals. The DAC is optimized for digital signal synthesis applications in wireless base stations and other communication applications. The power dissipation of the DAC is 78.21 mW at 498.05 MHz signal for a sampling rate of 1 GSPS with 1.8 V supply.