Fabrication of microvias for multilayer LTCC substrates

Advances in screen printing and photoimageable paste technologies have allowed low-temperature cofired ceramic (LTCC) circuit densities to continue to increase; however, the size of vias for Z-axis interconnections in multilayer LTCC substrates have been a limiting process constraint. In order to effectively exploit the 50-100-/spl mu/m line/spacing capabilities of advanced screen printing and photoimageable techniques, microvia technologies need to achieve 100 /spl mu/m and under in diameter. Three main steps in fabrication of microvias include via formation, via metallization or via fill, and layer-to-layer alignment. The challenges associated with the processing and equipment for the fabrication of microvias are addressed in this paper. Microvias down to 50 /spl mu/m in diameter with spacings as small as 50 /spl mu/m are achieved in 50-254-/spl mu/m-thick LTCC tape layers through the use of a mechanical punching system, whereas the minimum size of 75-/spl mu/m via/spacing is obtained using a pulse laser-drilling system in the LTCC tape layers with the same thicknesses as those for the punching test. The quality of punched microvias and laser-drilled microvias will be presented as well. Layer-to-layer alignment is crucial to the connection of vias in adjacent LTCC tape layers. Through a stack and tack machine with a three-camera vision system and an adjustable precision stage, less than 25-/spl mu/m layer-to-layer misalignment is achieved across a 114.3/spl times/114.3 mm (4.5/spl times/4.5 in) design area. In a six-layer LTCC test substrate (152/spl times/152/spl times/0.762 mm), microvias of 50, 75, and 100 /spl mu/m in diameter are successfully fabricated without the use of via catch pads. The cross section of fired microvias filled with silver conductor pastes at various locations of this substrate demonstrates a minor layer-to-layer misalignment in both X and Y directions across the substrate.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

A 35 ns 2K /spl times/ 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

High-voltage regulation and process considerations for high-density 5 V-only E/SUP 2/PROM's

A high density 5-V-only HMOS 1 FLOTOX E/SUP 2/PROM technology has been developed using stepper lithography and dry etching techniques. A 1.5-/spl mu/m minimum feature size and 0.5-/spl mu/m registration result in a FLOTOX cell with an area of 270 /spl mu/m/SUP 2/. This represents a 50% reduction of the original cell size. Equivalent endurance (10K cycles) and data retention (10 years) have been obtained. Improved critical dimension control has increased the uniformity of the new cell within the array. Junction leakage has been reduced by using an extended low-temperature anneal cycle. Circuit techniques have been developed to ensure full temperature range (-55-125/spl deg/C) operation. A capacitive voltage divider in a feedback loop, an E/SUP 2/ trimmable voltage reference, and a switched-capacitor RC network are employed to produce a temperature-stable programming pulse with a rising edge time constant of ~ 600 /spl mu/s. The programming voltage can be trimmed with an accuracy of /spl plusmn/ 0.5 V over a typical range of 19-24 V in order to match the requirements of the array. 16K and 64K 5-V-only E/SUP 2/PROMs with die sizes of 128 /spl times/ 182 mil and 223 X 278 mil have been fabricated.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-/spl mu/m digital CMOS process

This brief describes the design of a frequency synthesizer for 2.3/4.6-GHz wireless applications in a 0.35-/spl mu/m digital CMOS process. This synthesizer provides dual-band output signals by means of frequency doubling techniques. Output frequency of the proposed synthesizer ranges from 1.87-2.3 GHz, and 3.74-4.6GHz. This chip consumes a total power of 80 mW from a single 2-V supply, including 45 mW for dual-band output buffers. Core size is 2200 /spl mu/m/spl times/1600 /spl mu/m.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

This paper presents a single-chip mixed-signal IC for a hearing aid system. The IC consumes 270 /spl mu/A of supply current at a 1.1-V battery voltage. The presented circuit and architectural design techniques reduce the total IC power to 297 /spl mu/W, a level where up to 70 days of lifetime is achieved at 10 h/day for a small zinc-air battery. The measured input referred noise for the entire channel is 2.8 /spl mu/Vrms and the average THD in the nominal operating region is 0.02%. The jitter for the on-board ring oscillator is 147 ps rms. The chip area is 12 mm/sup 2/ in a 0.6-/spl mu/m 3.3-V mixed-signal CMOS process.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

Wide-band, low-noise, matched-impedance amplifiers in submicrometer MOS technology

Circuit design techniques for realizing wideband, low-noise, matched-impedance amplifiers in submicrometer MOS technology are discussed. A circuit configuration with two feedback loops has been fabricated in an experimental 1-/spl mu/m NMOS technology. The fabricated amplifier has an insertion gain of 16.35 dB, a -3-dB bandwidth of 758 MHz, a maximum input voltage standing-wave ratio (VSWR) of 2.45, a maximum output VSWR of 1.60, and an average noise figure of 6.7 dB (with reference to a 50-/spl mu/m source resistance) from 10 to 758 MHz.     

Performance analysis of 10-/spl mu/m-thick VCSEL array in fully embedded board level guided-wave optoelectronic interconnects

We introduce a simple and effective heat sink structure for thin-film vertical cavity surface emitting lasers (VCSELs) in fully embedded board level guided-wave interconnects. A 50% quantum efficiency increase is experimentally confirmed for the 10-/spl mu/m thin-film VCSELs. The thermal resistance of a 1 /spl times/ 12 embedded thin-film VCSEL array in printed circuit board (PCB) is further analyzed. The experimental results show an excellent match with the simulated results. The 10-/spl mu/m-thick VCSEL had the lowest thermal resistance and the highest differential efficiency compared to 250-, 200-, 150-, and 100-/spl mu/m-thick VCSELs. A substrate removed VCSEL can be used in fully embedded board level optical interconnects without special cooling techniques.     

Submicrometer Electron-Beam Direct Writing Technology for 1-Mbit DRAM Fabrication

A 1-Mbit DRAM with 0.5-/spl mu/m minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 /spl mu/m(sigma) and linewidth deviation of 0.018 /spl mu/m(sigma) in the fabrication.     

Convergence and loss bounds for Bayesian sequence prediction

The probability of observing x/sub t/ at time t, given past observations x/sub 1/...x/sub t-1/ can be computed if the true generating distribution /spl mu/ of the sequences x/sub 1/x/sub 2/x/sub 3/... is known. If /spl mu/ is unknown, but known to belong to a class /spl Mscr/ one can base one's prediction on the Bayes mix /spl xi/ defined as a weighted sum of distributions /spl nu/ /spl isin/ /spl Mscr/. Various convergence results of the mixture posterior /spl xi//sub t/ to the true posterior /spl mu//sub t/ are presented. In particular, a new (elementary) derivation of the convergence /spl xi//sub t///spl mu//sub t/ /spl rarr/ 1 is provided, which additionally gives the rate of convergence. A general sequence predictor is allowed to choose an action y/sub t/ based on x/sub 1/...x/sub t-1/ and receives loss /spl lscr//sub x(t)y(t)/ if x/sub t/ is the next symbol of the sequence. No assumptions are made on the structure of /spl lscr/ (apart from being bounded) and /spl Mscr/. The Bayes-optimal prediction scheme /spl Lambda//sub /spl xi// based on mixture /spl xi/ and the Bayes-optimal informed prediction scheme /spl Lambda//sub /spl mu// are defined and the total loss L/sub /spl xi// of /spl Lambda//sub /spl xi// is bounded in terms of the total loss L/sub /spl mu// of /spl Lambda//sub /spl mu//. It is shown that L/sub /spl xi// is bounded for bounded L/sub /spl mu// and L/sub /spl xi///L/sub /spl mu// /spl rarr/ 1 for L/sub /spl mu// /spl rarr/ /spl infin/. Convergence of the instantaneous losses is also proven.     

Low-power high-speed operation of submicron InP-InGaAs SHBTs at 1 mA

Scaling of submicron InP-InGaAs HBTs is investigated for low-power high-speed applications in mixed signal circuits. Device performance for transistors fabricated with a 0.5-/spl mu/m emitter width and varying emitter lengths are studied. The 0.5 /spl mu/m/spl times/2 /spl mu/m devices yielded excellent low-current RF performance, with an f/sub T/=173 GHz and an f/sub MAX/=187 GHz at 1 mA, the highest values reported for InP-based devices to date.     

Nonlinear analysis of GaN MESFETs with Volterra series using large-signal models including trapping effects

Nonlinearities in GaN MESFETs are reported using a large-signal physics-based model. The model accounts for the observed current collapse to determine the frequency dispersion of output resistance and transconductance. Calculated f/sub T/ and f/sub max/ of a 0.8 /spl mu/m/spl times/150 /spl mu/m GaN MESFET are 6.5 and 13 GHz, respectively, which are in close agreement with their measured values of 6 and 14 GHz, respectively. A Volterra-series technique is used to calculate size and frequency-dependent nonlinearities. For a 1.5 /spl mu/m/spl times/150 /spl mu/m FET operating at 1 GHz, the 1 dB compression point and output-referred third-order intercept point are 16.3 and 22.2 dBm, respectively. At the same frequency, the corresponding quantities are 19.6 and 30.5 dBm for a. 0.6 /spl mu/m/spl times/150 /spl mu/m FET. Similar improvements in third-order intermodulation for shorter gatelength devices are observed.     

On-chip test circuit for measuring substrate and line-to-line coupling noise

An on-chip test circuit has been developed to directly measure substrate and line-to-line coupling noise. This test circuit has been manufactured in a 0.35 /spl mu/m double-well double polysilicon CMOS process and consists of noise generators and switched-capacitor signal processing circuitry. On-chip analog-to-digital conversion and calibration are used to eliminate off-chip noise and to extend the measurement accuracy by removing system noise. A scan circuit is described that enables the noise waveform to be reconstructed. On-chip generators ranging in area from 0.25 /spl mu/m/sup 2/ to 1.5 /spl mu/m/sup 2/ produce noise at the receiver decreasing from 3.14 mV//spl mu/m to 0.73 mV//spl mu/m. Open and closed guard rings reduce the noise by 20% and 85%, respectively. Measurement of test circuits manufactured with an epitaxial process-5.5-/spl mu/m-thick epitaxy with 20 /spl Omega//spl middot/cm resistivity on top of a 120 /spl mu/m bulk with 0.03 /spl Omega//spl middot/cm-exhibits a frequency limit of 50MHz below which coupling is insensitive to substrate noise. The difference between experimental results and an analytic model of the line-to-line coupling capacitance ranges from 8.5% to 17.7% for different metal layers.     

Surface-emitting unstable-resonator lasers with integrated diffractive beam-forming elements

Grating-coupled surface-emitting semiconductor lasers have been integrated with focusing and spot array generating diffractive beam-forming elements. The lasers have an unstable resonator producing a 160-/spl mu/m-wide single spatial mode. The area of the outcoupler element is 160 /spl mu/m/spl times/240 /spl mu/m. For an outcoupler focusing at 500 /spl mu/m above the surface the spot size is 9 /spl mu/m/spl times/17 /spl mu/m The spot size is primarily limited by aberrations in the wavefront of the guided mode.     

Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3/spl times/3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 /spl mu/m/spl times/1 /spl mu/m or 1 /spl mu/m/spl times/70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by /spl sim/1000 electrons for the 1 /spl mu/m/spl times/1 /spl mu/m memory node cell and by 60 electrons for the 1 /spl mu/m/spl times/70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.