On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-μm CMOS technology exhibit a 100% delay increase in a long coupled line configuration     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Stacked CMOS circuits integrated in laser-recrystallized silicon films

Laser-recrystallized poly-silicon films are used as a substrate for the integration of MOS transistors and CMOS circuits. Ring oscillators and frequency divider circuits up to 100 transistors operate well with a yield of about 80%. For the integration of stacked CMOS circuits already tested bulk structures are covered with a dielectric layer and a poly-silicon film which is recrystallized at low temperature. The SOI integration technique, with a maximum temperature treatment of 960°C, is employed to manufacture the second active area as a 3-D technology. After the integration process SOI and bulk CMOS transistors operate independently at two different active levels.     

Process technology for radiation-hardened CMOS integrated circuits

A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.     

Investigation of gate oxide breakdown in CMOS integrated circuits

Investigation of gate oxide breakdown in CMOS integrated circuits, aimed at establishing its dependence on substrate doping (type and level) and its acceleration by an electric field, has been performed in this paper. In order to do this, time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric-breakdown (constant-voltage-stressed I-t) tests were carried out and the gate oxide breakdown histograms and electric field acceleration factor were determined and discussed in detail.     

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.     

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

Laser beam backside probing of CMOS integrated circuits

We have developed a new, fully integrated circuit timing analysis tool that provides measurements of electrical waveforms by direct access to the diffusion nodes through the backside of CMOS integrated circuits. The system, known as the IDS 2000, allows the device to be driven at full speed by a wide variety of testers. Utilising an actively modelocked infrared laser beam, the system can detect waveforms with ultrahigh bandwidth ( 10 GHz) from CMOS devices using stroboscopic sampling. The system has proven to be an powerful tool for design debug and failure analysis of flip chip packaged IC as well as any other packaged IC where the silicon side can be thinned and directly accessed.     

Noise in interconecction lines for submicrometer CMOS integrated circuits

The growing use of high performance portable systems is the main driving force for the significant advance in the technology of VLSI-CMOS integrated circuits. This advance has been carried out through scaling the transistor and interconnection sizes. However, as the transistor's size and interconnections are getting smaller, the signal integrity is becoming a critical issue. Therefore it is required to develop noise tolerant design circuit techniques in order to enhance the noise tolerance. In addition, these techniques should have a minimum impact on the circuit performance. In this paper, the noise immunity of dynamic logical circuits as the technology scales down is analyzed by using a reliable scaling scenario, and a new noise tolerant design technique is proposed. Prototype circuits implementing the proposed technique have been designed and fabricated. A one-bit carry look-ahead adder was designed using 0.35 mm CMOS-AMS technology. The experimental results show that the design technique here presented, results in an improvement of the ANTE by a factor of 3.4X when compared with the conventional TSPC, and an improvement by a factor of 1.7X when compared with the best noise tolerant technique currently published.     

Gate-level power and current simulation of CMOS integrated circuits

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser     

Multiple layers of CMOS integrated circuits using recrystallizedsilicon film

This letter presents a method to fabricate high performance three-dimensional (3-D) integrated circuits based on the conventional CMOS SOI technology. The first layer of transistors is fabricated on SOI and the second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI), using oxide as the interlayer dielectric. The LPSOI film is formed by the recrystallization of amorphous silicon through metal induced lateral crystallization (MILC). The grain size obtained by the LPSOI process is much larger than the transistors and the transistor performance is similar to those fabricated on the SOI layer. Three-dimensional (3-D) CMOS inverters have been demonstrated with p-channel devices stacking over the n-channel ones     

Overstress and electrostatic discharge in CMOS and BCD integrated circuits

The ESD qualification of the new technologies is obtained by testing different device structures an comparing the ESD robustness evaluated by means of different testing methods (HBM, MM, CDM and TLP). The influence of the layout parameters on the ESD robustness must also be characterized. In this paper we will present data concerning the ESD robustness of both 0.35 μm CMOS and 0.6 μm smart power (BCD5) protection structures. A study of the influence of layout parameters on the ESD robustness with different test methods (HBM, CDM and TLP) will be given. Failure analysis by means of electrical characterization, Emission Microscopy and SEM inspection will also been presented.     

Advanced failure detection techniques in deep submicron CMOS integrated circuits

The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability and observability (physically and electrically) and finally the required testing time. In the paper these points are discussed and different nowadays-promising techniques exposed. Complementarily to the logic output variable analysis (both value and delay) three efficient detection and localisation techniques can be considered that are contemplated in this work: the detection of light, heat and leakage currents due to the presence of failures. In most of the cases it is not possible to differentiate clearly, like was in the past, the production testing, the in-field testing, the test and the localisation of the failure, making each time closer the fields of testing and failure analysis.     

Coupling and crosstalk between high speed interconnects inultralarge scale integrated circuits

The advent of sophisticated lithographic techniques has made it possible to fabricate densely packed ultra-large-scale-integrated (ULSI) circuits. In these chips, interconnect lines are so narrow and spaced in such close proximity that signal from one line could easily get coupled to another, causing interference and crosstalk. A general theory to model coupling between optical interconnects (waveguides) and quantum-mechanical coupling between narrow and very closely spaced silicide interconnects embedded in dielectrics (SiO₂) is presented     

CMOS RF integrated circuits at 5 GHz and beyond

A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RFIC) technology in unprecedented ways. These pressures are stimulating novel solutions that allow RFICs to enjoy more of the benefits of Moore's law than has been the case in the past. In addition to regular raw transistor speed increases, the growing number of interconnect layers allows the realization of improved inductors, capacitors, and transmission lines. A deeper understanding of noise at both the device and circuit level has improved the performance of low noise amplifiers (LNAs) and oscillators. Finally, an appropriate raiding of circuit ideas dating back to the vacuum tube era enables excellent performance, even when working close to the limits of a technology. This paper surveys some of these developments in the context of low-power RF CMOS technology, with a focus on an illustrative implementation of a low-power 5-GHz wireless LAN receiver in 0.25-μm CMOS. Thanks to these recent advances in passive components and active circuits, the blocks comprising the receiver consume a total of approximately 37 mW. These blocks include an image-reject LNA, image-reject downconverter, and a complete frequency synthesizer. The overall noise figure is 5 dB, and the input-referred third-order intercept (IIP3) is -2 dBm. To underscore that 5 GHz does not represent an upper bound by any means, this paper concludes with a look at active circuits that function beyond 15-20 GHz, and a characterization of on-chip transmission lines up to 50 GHz, all in the context of how scaling is expected to shape future developments