基于电路三要素理论的五值计数器研究

本文提出六值代数,建立五值电路三要素理论(信号、网络和负载理论),作为定量研究五值电路的数学工具。在此基础上,首先用δ展开法由五值电路功能直接推出具有复位功能的五值反相器和动态D触发器的元件级结构。然后,对五值计数器进行研究,将其划分为五种类型,并设计出电路结构简单的具有复位功能的五值移位计数器。计算机模拟验证了上述理论和电路的正确性。     

电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。     

二值、多值和绝热电路通用的电路理论

本文提出二值、多值和绝热电路通用的电路理论,即电路三要素(信号,网络和负载)理论.为此首先提出普适的N+1值代数,推出网络转换定理和常用公式,用来直接由多值函数或触发器的特征方程推出它们的元件级结构.当N充分大时该理论可推广到绝热电路,从而在绝热约束条件下完成绝热电路定量分析与综合,用于诸如交叉耦合绝热触发器和绝热同步时序电路,由计算机模拟检验其正确性.     

关于三值维持阻塞JK触发器的研究

提出了一种具有在输出的三值维持阻塞ＪＫ触发器电路，描述了该触发器电路的设计，对由ＴＴＬ门电路组成的试验电路进行了计算机模拟和测试，结果表明，该触发器能实现预定的功能。     

钟控神经MOS管的改进及其在多值电路中的应用

首先对钟控神经MOS管进行研究,提出了相应的改进方法.然后采用此改进的钟控神经MOS管设计了一种新型多值触发器.与传统的触发器相比较,此多值触发器具有结构简单、速度快、功耗低等特点;而且无需改变电路结构就可实现不同基的多值触发器.PSPICE模拟证明了所设计的电路具有正确的逻辑功能.     

基于门控时钟技术的低功耗三值D型触发器设计

本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计.该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能.与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗.同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中.     

三值动态和静态广义时序机理论

该文在三值电路三要素理论的基础上提出了三值动态和静态广义时序机理论。首先找出三值状态图和电路方程间的关系,该关系既适用于静态电路,又适用于动态电路。对静态电路文中推导出各型三值触发器完整特性方程,它描述了触发器全时刻的行为,用以代替常规特性方程,使三值同步和异步时序电路统一。对动态电路该文用电容代替触发器存储三值信息,实现三值动态时序电路(特别是三值同步动态时序电路,属于非触发器式的时序电路)。因动态电路和静态电路主要差别是负载行为,故此可以在三值电路三要素理论和广义时序机理论下统一三值动态和静态,同步和异步时序电路。     

基于电路三要素理论的2-5混值/十值计数器研究

通过对2-5混值编码原理、电路三要素理论和N +1值代数理论的分析,定量研究了2-5混值门电路、触发器和带进位/借位的加减法计数器,最后设计了2-5混值/十值译码电路,使计数器输出为十值信号。与以往十值电路的设计方法相比较,此设计方案具有编码效率高、供电电压低等特点。计算机模拟验证了上述理论和依此理论设计的电路的正确性。     

低功耗四边沿触发器设计

根据在保持电路原有性能的前提下可通过降低时钟频率来降低系统功耗的原理和双边沿触发器的设计思想,本文将多值信号信息量大的优点应用于时钟网络上设计了基于三值时钟的四边沿触发器,消除了三值时钟的冗余跳变,从而通过降低时钟频率的方式达到降低功耗的目的。本文设计的四边沿触发器电路结构简单,既可以用于二值时序电路中也可以用于多值时序电路中。模拟结果表明,本文设计的四边沿触发器具有正确的逻辑功能且能有效地降低系统功耗。     

一种单锁存器CMOS三值D型边沿触发器设计

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计.该电路是通过时钟信号的上升沿后产生的窄脉冲使锁存器瞬时导通完成取样求值.所提出的电路较之以往设计具有更为简单的结构,三值双轨输出时仅需24个MOS管.计算机模拟结果验证了所提出的触发器具有正确的逻辑功能、良好的瞬态特性和更低的功耗.此外,该设计结构极易推广至基值更高的多值边沿触发器的设计.     

Design of ternary adiabatic multiplier on switch-level

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be obtained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ternary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are characterized with distinctive low power consumption.     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

对称三值电流型CMOS电路设计

本文应用开关信号理论,建立了采用对称三值逻辑的传输电流开关理论,该理论能指导从开关级设计对称三值电流型CMOS电路.应用该理论设计的对称三值电流型CMOS电路不仅具有简单的电路结构和正确的逻辑功能,而且能处理具有双向特性的信号.     

基于开关信号理论的三值电流型CMOS电路设计

本文应用开关信号理论对电流型CMOS电路中MOS传输开关管与电流信号之间的相互作用进行了分析,并提出了适用于电流型CMOS电路的传输电流开关理论。应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能,从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。     

A joint field/circuit model of line-to-ring coupling structures andits application to the design of microstrip dual-mode filters and ringresonator circuits

A joint field/circuit model is proposed in this paper to characterize a class of line-to-ring coupling structures for design and optimization of microstrip dual-mode filters and ring resonator circuits. The generic model is derived from field theory and presented in terms of circuit elements by applying a newly developed numerical deembedding technique called “short-open calibration” in a deterministic method-of-moments scheme. It provides a new design strategy for characterizing and optimizing electrical performance of the line-to-ring coupling structures. Such three-port topologies are explicitly formulated by using an equivalent network having circuit elements calculated by the proposed joint field/circuit model. Three microstrip tightly coupling geometries and their related ring resonators are studied with the extracted J-inverter susceptance parameters. Experiments are performed to validate the joint model and also show coupling characteristics of the three types of line-to-ring circuit for the design of ring resonators and dual-mode filters. With this new technique, an optimized microstrip dual-mode filter is successfully designed and the prediction agrees well with our measurements     

一种新型宽带平面和差网络

提出了一种新型的基于环形电桥结构的宽带平面和差网络。首先提出了一种新型的宽带微带/槽线转换结构,然后将该结构引入到传统的环形电桥结构中,优化设计了一种改进型环形电桥,最后采用四个改进的环形电桥构建了双平面和差网络。测试结果表明:在4.05～7.425GHz的频率范围内,八个端口的驻波均小于2,输入端口之间的隔离度均在20dB以上,输出端口之间的隔离度大于30dB,和端口的插入损耗小于0.5dB,差端口的零值深度小于-30dB。该和差网络具有性能优良、结构简单、制作成本低等优点,在宽频带单脉冲雷达天馈系统中得到了成功的应用。     

电路三要素理论和布尔代数失效原因分析

本文提出一个克服布尔代数失效的电路三要素理论。文中首先分析布尔代数在数字电路中失效的原因,接着证明开关运算定理等,它概括了文献中曾需一一证明的绝大多数开关运算等式,然后表明:数字电路的统一性既存在于门级和元件级电路间,也存在于各型元件级电路结构间,以及动态与静态电路间。此外,本文提出元件级电路设计的卡诺图方法和代数方法。     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

导通于放大状态的高速低压TTL与非门

本文在分析低压TTL门按传统方式实现高速的困难之后,首先提出一个利用射极跟随器钳位和反馈电路组成的导通于放大状态低压TTL电路,并设计出延迟时间tpd＜1ns的高速低压TTL与非门.接着进行电路分析和参数估算.用计算机模拟证明理论和电路的正确性.     

Wide-Band Equivalent Circuits of Microwave Planar Networks

A broad-band equivalent circuit of a generic microwave planar network is derived in terms of lumped constant elements. Contrary to previously proposed equivalent circuits, whose elements are strongly frequency dependent, the elements of the new one show only a smooth dependence on the frequency, because of the dispersion properties of microstrip structures. The equivalent circuit proposed is therefore easy to handle and is shown to be a useful basis for direct synthesis of planar structures. Good agreement with the theory is demonstrated by experiments performed on structures with different geometries up to 12.5 Ghz, by using equivalent circuits whose elements are assumed to be constant with the frequency.