直接数字波形合成中的镜频干扰分析

该文针对数字波形合成信号中的镜频干扰问题展开讨论,着重分析了镜频的形成机理及分布特点,说明了采样率对镜频干扰的影响。在此基础上定量分析了产生镜频干扰的采样率条件,并通过实验结果验证。该分析结果为数字波形合成中的采样率选取提供了新的理论依据。     

利用FPGA实现三相正弦直接数字频率合成器

利用FPGA芯片及D/A转换器,采用直接数字频率合成(DDS)技术,设计并实现了相位、频率可控的三相正弦信号发生器.正弦调制波的产生采用查表法,仅将1/4周期的正弦波数据存入ROM中,减少了系统的硬件开销.仿真和电路测试表明,输出波形完全达到了技术要求,证明了设计的正确性和可行性.     

论DAC性能对数字合成波形失真的影响

任意信号发生器是当前国内外在检测仪器方面研究的热点之一。本文主要从理论上分析了转换ＤＡＣ单元在信号合成过程中,合成信号产生的失真以及小失真的办法。     

基于FPGA的直接数字波形合成宽带信号源的设计与实现

提出一种改进的波形存储直读法产生宽带雷达线性调频信号的设计方案.以单片高速FPGA取代以往设计中使用的DSP FPGA作为系统的控制核心,简化系统结构.外围接口通用化、模块化,可产生带宽200MHz以内、时宽800μs以内的任意LFM信号.应用预失真技术,产生的宽带信号线性调频相位失真小于±1度,线性调频脉冲顶部不平坦度小于0.5dB,采用Hamming加权后脉冲压缩峰值旁瓣比大于38dB.     

软件无线电中直接波形合成的研究

直接数字频率合成（DDS）是一种新型的频率合成技术。介绍了如何利用DDS技术来产生调频波形及其他的数字调制波形;阐述了一种新的适合于软件无线电实现的算法,即采用预先计算后存贮在贮存器中的波形来代替实时运算,直接合成数字调制波形（DWS）;研究了一种压缩查找表的方法。此外,还对此算法在实现过程中遇到的截断误差、运算量和存贮量的问题进行了探讨。对于所提及的算法,给出了仿真结果。     

基于FPGA实现的任意波形产生器

介绍了DDS的原理和FPGA的特点，并在此基础上描述了基于FPGA的DDS的硬件和软件设计方案。     

直接数字频率合成的DAC毛刺杂散分析

从DAC毛刺的形成特点出发，建立了DAC毛刺的简化数学模型，对其进行了初步的定量分析，得到了它在直接数字频率合成输出频谱中杂散分量的表达式，并介绍了两种用于消除毛刺影响的方法。     

ADI推出集成复杂波形生成功能的DAC

ADI公司最近发布了四通道、12位／单通道、14位的180MSPS波形发生器AD9106／AD9102,均片内集成静态随机存取存储器（SRAM）和直接数字频率合成器（DDS）,用于复杂波形生成。     

应用于数字阵列的多通道波形产生系统设计

直接数字频率合成（DDS）是数字阵列雷达（DAR）实现收发数字波束形成的关键技术之一。给出了一种基于DDS技术的多通道波形产生系统的设计方案,该方案在25cm×12cm的PCB板上实现了波形产生、波形捷变与幅相控制的系统集成设计。该系统能同时产生16路频率、幅度和相位独立控制的中频雷达信号,满足数字阵列雷达对收发阵列单元的高集成度、小型化、低成本和多功能的要求;系统实现的主要技术指标为：信号带宽1～120MHz可变,通道隔离度大于60dBc,窄带脉内信噪比大于65dBc,满足数字阵列雷达技术指标的要求。     

采用低端FPGA实现直接数字频率合成的优化设计

当前大多数DDS实现方案要满足工程要求,成本和复杂度都很高。为此,提出一种基于 相位合成利用低端FPGA实现DDS的优化设计方案,介绍了其硬件和软件实现。 实测结果表明,所设计的DDS功耗低,输出信号频率稳定度高,频率转换速度快,输出频 点灵活,任意设置信号波形效果好,能普遍应用于通信调制、仪表检测、信号发生中。     

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-$mu$m SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 $Omega$ loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.      

Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method

A dynamic element-matching (DEM) method, i.e., randomized thermometer coding (RTC), for low-cost current-steering digital-to-analog converter (DAC) design is proposed. The proposed RTC method exhibits randomized starting-element selection, consecutive-element selection, and low-element switching activity. It can be used to significantly suppress the harmonic distortion caused by a large mismatch of small-area transistors, and, thus, very low cost DACs can be realized. With the proposed RTC, a 14-bit current-steering DAC is implemented in a 1P6M 0.18- $muhbox{m}$ 1.8-V CMOS process. The measured spurious-free dynamic range (SFDR) exceeds 80 dB. The measurement results showed that RTC improves the SFDR by more than 16 dB. The DAC has an active area of less than 0.28 $hbox{mm}^{2}$. The proposed DAC achieves a smaller active area than state-of-the-art 12- to 14-bit DACs.      

Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic

This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been used in the past for lower-speed (i.e. ≤12.8 Gbps) applications. However, success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost (off-the-shelf) components are used so that the method can be applied to test scenarios requiring many high-speed channels. Analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method. A Development Platform is also described that facilitates individual module characterization and integration of multiple modules to form customized test systems.     

高速数模转换芯片DAC5682在3G数字中频发射机中的应用

文章给出了一种基于DAC5682的3G数字中频发射机的实现方案，通过与传统模拟发射机实现方案的对比，指出了基于软件无线电数字中频化思想的数字中频发射机实现方案的优势所在。同时也研究了DAC5682的工作原理，介绍了DAC5682的主要技术特点，给出了其在3G系统应用中的典型配置，并给出了典型应用电路，最后指出了DAC5682在实际应用中应该注意的问题。     

具有目测指示的数字金属探测器

本文给出的数字金属探测器提供目测指示并辨别黑色和有色金属.     

用于高精度DAC测试的数字正弦波发生器

介绍了一种用于高精度DAC测试的数字正弦波发生器.该发生器应用坐标轴旋转数字算法 (CORDIC),计算出输入角度的三角函数值;同时设置相应的控制单元,可产生幅度和频率皆可调节的实时数字正弦波.电路在Xilinx的FPGA开发板ML401上实现,并利用SoPC技术提供控制幅度和频率的界面.设计的发生器已应用于高精度(20位)音频DAC测试,产生的SNR大于120 dB,可满足测试要求.     

Digital compensation of DAC mismatches in multibit delta-sigma ADCs

A digital compensation technique to overcome the effects of the digital-to-analogue converter (DAC)'s mismatches in multibit delta- sigma modulators is described. The technique is purely digital, does not require the injection of a pilot signal and is compatible with binary-weighted element DACs. Simulation results confirm the validity of the compensation technique for a four-bit, fifth-order lowpass modulator with an oversampling ratio of 12 and 1% mismatch in the DAC elements. The compensated modulator exhibits a peak signal- to-noise-and-distortion ratio of 74.5 dB; that is within 0.5 dB of the ideal system without mismatch.     

数字电源提供多种配置方式和应用灵活性

传统的模拟电源无论在拓扑结构、器件、效率、功能上都日臻完善，应用也极为广泛，并且有大量的工程技术人才熟悉和正在设计使用模拟电源。但模拟电源最大的缺点是缺乏灵活性，在应用的需求变化时，需要花很多时间进行重新设计、验证和测试。     

A Low-Cost Digital Matched Filter for Arbitrary Constant-Envelope Spread-Spectrum Waveforms

In this paper a noncoherent digital matched filter (DMF) with binary quantization is presented which shows good performance for arbitrarily angle modulated constant-envelope waveforms having large time-bandwidth products. The considered DMF represents an extension of the noncoherent DMF with one-bit digitization suggested previously by Turin for binary PSK signals. Analysis of the filter performance in the presence of white Gaussian noise results in a general expression which allows the output SNR of both DMF's to be calculated for any spread-spectrum waveform. Evaluating this expression reveals that the extended DMF can be matched to arbitrary waveforms having constant envelopes in such a way that the SNR loss with reference to the corresponding analog matched filter is less than 2.87 dB. The degradation is as low as 1.96 dB for waveforms with biphase or quadriphase signal samples such as binary PN-PSK, PNQPSK, and offset-PN-QPSK, but also PN-MSK. If both DMF's are applied to waveforms having complex valued envelopes, the extended DMF may outperform Turin's DMF by as much as 3 dB.     

附有数字信号输出用于压力测量的低成本电路

介绍了一种用于压力测算并附有数字信号输出的低成本电路,这种电路由脉宽调制器和数字频率微分器组成,它能将传感器电阻的相对变换量线性地转换成输出信号的脉宽变换,该电路精度高、受温度影响小,重复性好。