An All-Digital RF Signal Generator Using High-Speed $DeltaSigma$ Modulators

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm² (0.15 mm² for the active area).     

Adaptive Blocker Rejection Continuous-Time $Sigma Delta $ ADC for Mobile WiMAX Applications

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a worldwide inter-operability for microwave access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 mus, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving - 22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metal-insulator-metal (MIM) capacitor, CMOS technology, occupying 1.5 times 0.9 mm² silicon area.     

A 9 mW Highly-Digitized 802.15.4 Receiver Using Bandpass $SigmaDelta$ ADC and IF Level Detection

A low power (9 mW) highly-digitized 2.4 GHz receiver for sensor network applications (IEEE 802.15.4 LR-WPAN) is realized by a 0.18 $mu{rm m}$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time (CT) bandpass $SigmaDelta$ modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $SigmaDelta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range (DR) of the overall system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.      

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $Delta Sigma$ ADC in 90 nm CMOS

This paper describes the results of an implementation of a high speed $Delta Sigma$ ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The $Delta Sigma$ ADC is based on a switched-capacitor fourth-order single-loop $Delta Sigma$ modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated $Delta Sigma$ ADC and the digital signal processing block occupy 0.53$~$mm$^2$ and 0.09 mm$^{2}$, and consume 11.76 mW per channel.      

A 20 to 24 GHz $+$16.8 dBm Fully Integrated Power Amplifier Using 0.18 $mu{rm m}$ CMOS Process

A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm², which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm², which is the smallest one compared to all reported paper.     

An 11 mm$^{2}$ , 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12$ mu$ m CMOS

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm² in a 0.12 mum CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.     

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable- $g_{m}$ opamp. The ADC is implemented in 0.18 $muhbox{m}$ CMOS technology and occupies a die area of 0.86 ${hbox{mm}}^{2}$. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, ${-}$66.2 $~$dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply.      

A 10$sim$ 15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration

Floating-point analog-to-digital converter (FADC) utilizes an up-front variable-gain amplifier (VGA) to enhance its low-level resolution. Although it is a single-path system, varying gain by switching circuit elements in and out modulates the gain and offset as in the multi-path time-interleaved ADC. For high-speed operation at all gain settings, a constant-bandwidth switched-capacitor VGA is implemented with variable-bandwidth opamps, and its gain and offset are digitally calibrated in background using signal-dependent pseudo-random noise (PN) dithering and chopping techniques. A three-stage VGA adjusts its gain instantly from $times$ 1 to $times$ 32 depending on the sampled input level, and improves the INL of a 10-bit ADC from 24 to 0.9 least significant bits (LSBs) at a 15-bit level for the low-level input. The resulting 10 $sim$ 15-bit 60-MS/s ADC needs no input sample-and-hold (S/H) stage, and achieves a system noise of $-$80 dBFS with a gain set to $times$ 32. A prototype chip in 0.18-$muhbox{m}$ CMOS occupies an active area of $3.0times 2.0 hbox{mm}^{2}$ , and consumes 300 mW at 1.8 V including digital calibration logic.      

$n$ -SIFT: $n$ -Dimensional Scale Invariant Feature Transform

We propose the $n$ -dimensional scale invariant feature transform ( $n$-SIFT) method for extracting and matching salient features from scalar images of arbitrary dimensionality, and compare this method's performance to other related features. The proposed features extend the concepts used for 2-D scalar images in the computer vision SIFT technique for extracting and matching distinctive scale invariant features. We apply the features to images of arbitrary dimensionality through the use of hyperspherical coordinates for gradients and multidimensional histograms to create the feature vectors. We analyze the performance of a fully automated multimodal medical image matching technique based on these features, and successfully apply the technique to determine accurate feature point correspondence between pairs of 3-D MRI images and dynamic $3{rm D} + {rm time}$ CT data.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

Highly Linear Tunable CMOS $Gm{hbox{-}}C$ Low-Pass Filter

A comprehensive analysis of tunable transconductor topologies based on passive resistors is presented. Based on this analysis, a new CMOS transconductor is designed, which features high linearity, simplicity, and robustness against geometric and parametric mismatches. A novel tuning technique using just a MOS transistor in the triode region allows the adjustment of the transconductance in a wide range without affecting the voltage-to-current conversion core. Measurement results of the transconductor fabricated in a 0.5- mum CMOS technology confirm the high linearity predicted. As an application, a third-order Gm-C tunable low-pass filter fabricated in the same technology is presented. The measured third-order intermodulation distortion of the filter for a single 5-V supply and a 2-V_pp two-tone input signal centered at 10 MHz is -78 dB.     

Density of States-Based DC $I$– $V$ Model of Amorphous Gallium–Indium–Zinc-Oxide Thin-Film Transistors

The density of states (DOS)-based DC I-V model of an amorphous gallium-indium-zinc oxide (a-GIZO) thin-film transistor (TFT) is proposed and demonstrated with self-consistent methodologies for extracting parameters. By combining the optical charge-pumping technique and the nonlinear relation between the surface potential (phiS) and gate voltage (V _GS), it is verified that the proposed DC model reproduces well both the measured V _GS-dependent mobility and the I _DS-V _GS characteristics. Finally, the extracted DOS parameters are N _TA = 4.4 times 10¹⁷ cm^-3 middot eV^-1, N _DA = 3 times 10¹⁵ cm^-3 middot eV^-1, kT _TA = 0.023 eV, kT _DGA = 1.5 eV, and EO = 1.8 eV, with the formulas of exponential tail states and Gaussian deep states.     

Plasmon-Waveguide Interband Cascade Lasers Near 7.5 $mu$ m

Broad-area plasmon-waveguide interband cascade lasers with emission wavelengths near 7.5 mu m were demonstrated at temperatures up to 121 K in continuous-wave mode. Their threshold current densities and voltages varied from 72 A/cm² and 2.1 V at 84 K to 400 A/cm² and 2.7 V at 121 K, showing very efficient use of bias voltage (e.g., voltage efficiency of about 90% at 84 K) at this long wavelength. These plasmon-waveguide lasers also operated in pulsed mode at temperatures up to 165 K with emission wavelengths near 7.6 mum and threshold current density of 1100 A/cm².     

Analysis of Clock-Jitter Effects in Continuous-Time $Delta Sigma $ Modulators Using Discrete-Time Models

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) $Delta Sigma $ modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT $Delta Sigma $ modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the $Delta Sigma $ modulator.      

A 67 dBm $OIP_{3}$ Multistacked Junction Varactor

A multistacked varactor is presented for ultra-linear tunable radio frequency applications. The varactor elements are applied in anti-series configuration and are characterized by an “exponential” $C$- $V _{R}$ relationship. Third-order intermodulation ($IM_{3}$) is cancelled through proper harmonic loading of the terminals of the anti-series configuration. Multiple stacking is used to further increase the power handling and to minimize the remaining fifth-order distortion. The measured output intercept point ($OIP_{3}$ ) at 2 GHz is $ > 67~{rm dBm}$ for modulated signals up to 10 MHz bandwidth, while providing a capacitance tuning ratio of 3:1 with an average quality factor of 40 and maximum control voltage of 10 V.      

Design and Realization of Wide-Band-Gap ($sim$ 2.67 eV) InGaN p-n Junction Solar Cell

The design of coherently strained InGaN epilayers for use in InGaN p-n junction solar cells is presented in this letter. The X-ray diffraction of the epitaxially grown device structure indicates two InGaN epilayers with indium compositions of 14.8% and 16.8%, which are confirmed by photoluminescence peaks observed at 2.72 and 2.67 eV, respectively. An open-circuit voltage of 1.73 V and a short-circuit current density of 0.91 mA/cm² are observed under concentrated AM 0 illumination from the fabricated solar cell. The photovoltaic response from the InGaN p-n junction is confirmed by using an ultraviolet filter. The solar cell performance is shown to be related to the crystalline defects in the device structure.     

Optimal $ Sigma Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis

This paper presents a comparative study of $Sigma Delta$ modulators for use in fractional-$ {N}$ phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.