Fast template placement for reconfigurable computing systems

This article presents fast online placement methods for dynamically reconfigurable systems, as well as offline 3D placement algorithms for statically reconfigurable architectures     

The case for reconfigurable hardware in wearable computing

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.     

A process-driven computing model for reconfigurable semiconductor manufacturing

Reconfigurability is essential for semiconductor manufacturing systems to remain competitive. Reconfigurable systems avoid costly modifications required to change and adapt to changes in product, production and services. A fully automated, collaborative, and integrated while reconfigurable manufacturing system proves cost-effective in the long term and is a promising strategy for the semiconductor manufacturing industry. However, there is a lack of computing models to facilitate the design and development of control and management systems in a truly reconfigurable manner. This paper presents an innovative computing model for reconfigurable systems and controlled manufacturing processes while allowing for the integration of modern technologies to facilitate reconfiguration, such as radio frequency identification (RFID) and reconfigurable field programmable gate array (FPGA). Shop floor manufacturing activities are modeled as processes from a business perspective. A process-driven formal method that builds on prior research on virtual production lines is proposed for the formation of a reconfigurable cross-facility manufacturing system. The trajectory of the controlled manufacturing systems is optimized for on-demand production services. Reconfigurable process controllers are introduced in support of the essential system reconfigurability of future semiconductor manufacturing systems. Implementation of this approach is also presented.     

支持动态可重构硬件透明编程的预配置调度

面向微处理器和可编程器件加速器的混合异构多核体系结构的可重构计算环境,采用程序员熟悉的函数描述格式,在运行时根据软硬件划分的结果,动态实现到软件函数实体代码或者硬件函数实现电路的连接。为降低重配置开销,提高系统性能,统计了各个硬件函数的调用次数和次序,并结合其运行时间和硬件面积等信息,设计了一种预配置算法,尽量使配置和计算能够重叠处理,从而缩短系统的整体运行时间,获得更大性能加速。     

High-performance computing using a reconfigurable accelerator

The paper introduces the MoM-3 as a reconfigurable accelerator for high performance computing at a moderate price. By using a new machine paradigm to trigger the operations in the MoM-3, this accelerator is especially suited to scientific algorithms, where the hardware structure can be configured to match the structure of the algorithm. The MoM-3 efficiently uses reconfigurable logic devices to provide a fine-grain parallelism, and multiple address generators to have the complete memory bandwidth free for data transfers (instead of fetching address computing instructions). Speed-up factors up to 82, compared to state-of-the-art workstations, are demonstrated by means of an Ising spin system simulation example. Adding the MoM-3 as an accelerator enables achievement of supercomputer performance from a low-cost workstation.     

Continuity aspects of embedded reconfigurable computing

In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.     

Self-adaptive and reconfigurable distributed computing systems

In recent time, the applications of biologically-inspired computing models into various domains of computing fields have gained attention due to a set of advantages. The bio-inspired distributed computing paradigm offers benefits such as, self-detection and self-reconfiguration capabilities of the computing systems. The large scale distributed systems suffer from the arbitrary failure of nodes and dynamic formation of network partitions at any point of time. This paper proposes a novel membrane algorithm for self-detection and self-reconfiguration of large distributed systems on the event of arbitrary node failures resulting in network partitioning. The algorithm is distributed in nature and, it is designed based on the hybridization of biological membrane computing model and cell-signaling mechanisms of biological cells. This paper presents the problem definition, design and analysis of the algorithm. The performance of the algorithm is evaluated through simulation. A detailed comparative analysis of the algorithm with respect to the other contemporary algorithms is presented.     

Optimization of reconfigurable optically interconnected systems for parallel computing

This paper examines the use of an FPGA to circumvent the redundancy that may occur in free-space optically interconnected systems. We believe this paper presents solutions to the mapping of emitters and detectors onto an optoelectronic interface in order to perform an efficient connection topology. We report a novel versatile arrangement of the input/output optical interface and a straightforward algorithm for the implementation of a completely connected topology. Both utilize the reconfigurable potential of the FPGA to ease the design constraints on the optical system.     

A reconfigurable computing framework for multi-scale cellular image processing

Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. These architectures are a good match for many image and video processing applications and can be substantially accelerated with Reconfigurable Computers. We present a flexible software/hardware framework for design, implementation and automatic synthesis of cellular image processing algorithms. The system provides an extremely flexible set of parallel, pipelined and time-multiplexed components which can be tailored through reconfigurable hardware for particular applications. The most novel aspects of our framework include a highly pipelined architecture for multi-scale cellular image processing as well as support for several different pattern recognition applications. In this paper, we will describe the system in detail and present our performance assessments. The system achieved speed-up of at least 100× for computationally expensive sub-problems and 10× for end-to-end applications compared to software implementations.     

Performance analysis challenges and framework for high-performance reconfigurable computing

Reconfigurable computing (RC) applications employing both microprocessors and FPGAs have potential for large speedup when compared with traditional (software) parallel applications. However, this potential is marred by the additional complexity of these dual-paradigm systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications’ increased complexity. In this paper, we explore challenges and present new techniques in automated instrumentation, runtime measurement, and visualization of RC application behavior. We also present ideas for integration with conventional performance analysis tools to create a unified tool for RC applications as well as our initial framework for FPGA instrumentation and measurement. Results from a case study are provided using a prototype of this new tool.     

Seamless hardware-software integration in reconfigurable computing systems

Ideally, reconfigurable-system programmers and designers should code algorithms and write hardware accelerators independently of the underlying platform. To realize this scenario, the authors propose a portable, hardware-agnostic programming paradigm, which delegates platform-specific tasks to a system-level virtualization layer. This layer supports a chosen programming model and hides platform details from users much as general-purpose computers do. We introduce multithreaded programming model for reconfigurable computing based on a unified virtual-memory image for both software and hardware application parts. We also address the challenge of achieving seamless hardware-software interfacing and portability with minimal performance penalties.     

高性能计算中应用驱动的多DSP处理器阵列研究*

数字信号处理（DSP）芯片是一种特别适合于进行数字信号处理运算的微处理器,高性能计算由于大数字运算量和高速处理的要求,因而非常适合于DSP的应用。本文针对工业CT图像的三维重建这一典型应用,分析了DSP在高性能计算中的应用特点、方式和效果,提出了一种动态可重构的多DSP处理器阵列的设计方法。最后通过软硬件仿真验证了DSP在高性能计算中的性能和多DSP设计方案的可行性。     

A programmable spike-timing based circuit block for reconfigurable neuromorphic computing

A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems m CMOS technology to demonstrate the functionality of the circuits in silicon.     

A fast algorithm for computing a histogram on reconfigurable mesh

The reconfigurable mesh captures salient features from a variety of sources, including the content addressable array parallel processor, the CHiP, the polymorphic-torus network and the bus automaton. It consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns between the processors. In this paper, we present a fast algorithm for computing the histogram of an N×N image with h grey levels in O(min{√h+log*(N/h),N}) time on an N×N reconfigurable mesh assuming each PE has a constant amount of local memory. This algorithm runs on the PARBUS and MRN/LRN models. In addition, histogram modification can be performed in O(√h) time on the same model. A variant of out algorithm runs in O(min{√h+log log(N/h),N}) time on an N×N RMESH in which each PE has constant storage. This result improves the known time and memory bounds for histogramming on the RMESH model     

High-level debugging of distributed systems: The behavioral abstraction approach

Most extant debugging aids force their users to think about errors in programs from a low-level, unit-at-a-time perspective. Such a perspective is inadequate for debugging large complex systems, particularly distributed systems. In this paper, we present a high-level approach to debugging that offers an alternative to the traditional techniques. We describe a language, edl, developed to support this high-level approach to debugging and outline a set of tools that has been constructed to effect this approach. The paper includes an example illustrating the approach and discusses a number of problems encountered while developing these debugging tools.     

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has moved on the number of cores. Consequently, the fundamental feature of system designs and their associated design flows and tools need to change, so that, to support the scalable parallelism and the design portability. The same feature can be exploited to design reconfigurable hardware, such as FPGAs, which leads to rethink the mapping of sequential algorithms to HDL. The sequential programming paradigm, widely used for programming single processor systems, does not naturally provide explicit or implicit forms of scalable parallelism. Conversely, dataflow programming is an approach that naturally provides parallelism and the potential to unify SW and HDL designs on heterogeneous platforms. This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems. Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.     

Cyclic coding algorithms under MorphoSys reconfigurable computing system

This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) [1], [2], [3], [4], [5]. The paper addresses the results obtained when using RC in mapping algorithms pertaining to digital coding in relation to previous research [6], [7], [8], [9], [10]. The chosen algorithms relate to cyclic coding techniques, namely the CCITT CRC-16 and the CRC-16. A performance analysis study of the M1 RC system is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For comparison purposes, three other systems were used to map the same algorithms showing the advantages and disadvantages of each compared with the M1 system. The algorithms were run on the 8×8 RC (reconfigurable) array of the M1 (MorphoSys) system; numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations.     

Portable library development for reconfigurable computing systems: A case study

Portable libraries of highly-optimized hardware cores can significantly reduce the development time of reconfigurable computing applications. This paper presents the tradeoffs and challenges in the design of such libraries. A set of library development guidelines is provided, which has been validated with the RCLib case study. RCLib is a set of portable libraries with over 100 cores, targeting a wide range of applications. RCLib portability has been verified in three major High-Performance reconfigurable computing architectures: SRC6, Cray XD1 and SGI RC100. Compared to full-software implementations, applications using RCLib hardware acceleration cores show speedups ranging from one to four orders of magnitude.